Showing papers on "Control reconfiguration published in 1981"

Information storage in a decentralized computer system

Abstract: This paper describes an architecture for shared information storage in a decentralized computer system The issues that are addressed include: naming of files and other objects (naming), reliable storage of data (stable storage), coordinated access to shared storage (transactional storage), location of objects (location), use of multiple copies to increase performance, reliability and availability (replication), dynamic modification of object representations (reconfiguration), and storage security and authentication (protection) A complete model of the architecture is presented, which describes the interface to the facilities provided, and describes in detail the proposed mechanisms for implementing them The model presents new approaches to naming, location, replication, reconfiguration, and protection To verify the model, three prototypes were constructed, and experience with these prototypes is discussed The model names objects with variable length byte arrays called references References may contain location information, protection guards, cryptographic keys, and other references In addition, references can be made indirect to delay their binding to a specific object or location The replication mechanism is based on assigning votes to each copy of a replicated object The characteristics of a replicated object can be chosen from a range of possibilities by appropriately choosing its voting configuration Temporary copies can be easily implemented by introducing copies with no votes The reconfiguration mechanism allows the storage that is used to implement an object to change while the system is operating A client need not be aware that an object has been reconfigured The protection mechanism is based on the idea of sealing an object with a key Sealed objects can only be unsealed with an appropriate set of keys Complex protection structures can be created by using such operators as Key-Or and Key-And The protection mechanism can be employed to create popular protection policies such as capabilities, access control lists, and information flow control

Identification apparatus for use in a controller to facilitate the diagnosis of faults

Abstract: A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

The architecture of Tandem's NonStop system

Abstract: A Tandem T16 computer system is a network of up to 256 nodes. Each node consists of two to sixteen processors. The system had three major design goals: (1) Continuous data availability. (2) Modular growth by adding processing elements to a node. (3) Support of a network of geographically distributed nodes for on-line transaction processing. This talk will sketch Tandem's approach to continuous data availability. At the hardware level, NonStop is achieved by designing a single-fault tolerant system. A Tandem system has two or more modules and paths for each function. In addition, the system design addresses issues such as power failure, on-line maintenance, and reconfiguration.

Design of a Time-Optimal Feedback Controller for Systems with Delay in Control

Abstract: Time-optimal feedback controllers are studied for systems with delay in control. The control input is assumed to be bounded. Design methods are presented for continuous-time as well as discrete-time controllers. Sensitivities of the control system performance due to mismatches between the model and the plant are also studied. Finally, an adaptive time-optimal feedback controller is investigated which is capable of updating model parameters during normal system operation.

Multilevel load frequency control (a perturbational approach)

Abstract: A two-level control scheme for the load frequency control of a multi-area power system utilizing certain possible beneficial aspects of interconnections is described in this paper. The problem is identified as the determination of the necessary equivalent perturbation on the control distribution matrix to provide the corrective control.

Adaptable pipeline system with dynamic architecture

Abstract: This paper describes a pipeline system with dynamic architecture that performs cost-effective adaptations to the algorithm being executed. The system performs the following pipeline adaptations: (1) the number of stages in the pipeline changed to allow each instruction to activate the number of stages that matches the number of operations it realizes; (2) the operation sequences in the pipeline modified to allow any sequence of operations to execute without reconfiguration and thus eliminate the time overhead caused by this reconfiguration; and (3) the operation time in each stage adjusted to the minimum required for that operation because it may shorten the time of the total operation. This paper also discusses fast and flexible information exchanges between pipeline stages that can be done while the pipeline is working. Namely, each pipeline stage Ci may obtain during pipeline computations a temporary result that was computed by any other stage Cj. It is shown that such a pipeline may be organized from DC groups and thus be amenable to LSI implementation.

IBM contributions to computer performance modeling

Abstract: Performance modeling can be used throughout the life of a computer system, from initial design, through implementation, configuration (and reconfiguration) and even tuning. Performance models are usually solved by numerical techniques, where possible, and by simulation, otherwise. This paper summarizes IBM's contributions to performance modeling and the solution of performance models.

Self-Diagnosing Cellular Implementations of Finite-State Machines

Abstract: Cellular spaces are shown to possess properties favorable to reconfiguration. As a first step in the direction of reconfigurable cellular spaces, this paper demonstrates the implementation of arbitrary finite-state machines in self-diagnosing cellular spaces. The results cover single cell failures caused by erroneous state transitions or by erroneous outputs. One of the attractive features of the implementation is the absence of any hard core components. As an intermediate step, it is shown how to transform any given cellular space into a self-diagnosing cellular space. The results demonstrate that the control structure (which is a finite-state machine) of any computing device can be implemented as a self-diagnosing entity without hard core.

A Continuously Reconfiguring Multi-Microprocessor Flight Control System.

Abstract: : Recent research at the US Air Force Wright Aeronautical Laboratories (Flight Dynamics Lab) has resulted in the development of a promising microprocessor-based flight control system design This system is characterized by a collection of cooperatively autonomous distributed microcomputers interconnected by an arbitrary number of common serial multiplex busses Each processor in the system independently determines its assignments using a simple algorithm that dynamically redistributes system functions from processor to processor in a never-ending process of reconfiguration This approach offers several benefits in terms of system reliability, and the architecture in general incorporates many state-of-the-art features which promise improved system throughput, expandability, and above all, ease of programming

A dynamically reconfigurable microprocessor architecture

Abstract: This thesis examines the use of bit slice microprocessors in providing a multicomputer system with dynamic reconfiguration capabilities. These capabilities allow reconfiguration, under software control, of the system hardware into a variable number of processors of different characteristics (such as word size and instruction set). There are many potential uses of such capabilities in the areas of multiprogramming, parallel processing, and fault tolerant systems. The reconfiguration capability introduces a number of issues concerning processor function modularization, that do not arise in fixed architectures. The thesis examines these issues and shows potential processor modules that are realizable with current LSI technology. A dynamically reconfigurable architecture has problems in providing efficient connections between the processors and shared input, output, and file storage devices. This thesis examines an asynchronous bus structure and associated bus window devices that solve these problems. The structure examined equips each processor with a local bus for memory and dedicated devices, with access to one or more global shared resource buses. The structure supports processor and direct memory access device controlled data transfers, both intra- and inter-bus, as well as intra-bus interrupts and interrupt transfers between buses. This thesis provides details of the bus lines, the bus protocols, and the operation of the various bus windows. It examines the problem of potential deadlock, and its resolution, and the problem of equitable bus sharing in periods of high bus contention.

Industrial complex multiprocessor control system - uses microprocessor to detect and correct system fault by modifying configuration

Abstract: The control system has at least two central processors and a number of sensors coupled to the mfg. process connected to the input/output circuits for the processors. The input/output circuits are coupled to the processors via respective switching devices. A microprocessor responds to a fault in the control system and allows the configuration to modified to correct the detected fault with min. interruption of the mfg. process. The control system is put into hold when the integrity of the central processors is being checked by the microprocessor and during any subsequent restructuring of the system configuration. the system is reactivated after reconfiguration, and the microprocessor is returned to a monitoring phase.

Adaptive power management a hierarchical/distributed system

Abstract: The automatic control of electrical system (ACES) for aircraft shipboard applications was first demonstrated at the Westinghouse Aerospace Electrical Division in 1970 [4]. This system was implemented on a single computer which controlled the hardware directly with discrete signals. Presently Hierarchical and Distributed computer architectures are being evaluated [3, 14], to perform the ACES task. Westinghouse is pursuing a combined Hierarchical/Distributed architecture for its Adaptive Power Management (APM) system [5]. The Hierarchical network performs system control, conflict resolution, and top level resource monitoring and adaption/reconfiguration. The Distributed network performs the system Input/Output functions, all direct control and coordination of the peripherial hardware and the adaption/reconfiguration of their resource/control tables (see Figure 10). In addition, APM complies with the Air Forces requirement to use the standard DAIS AN/AYK-15A processor [10, 11]; the standard higher order programming language as defined in MIL-STD-1589 [12], and interface and data bus multiplex system standard MIL-STD-1553B [8, 9].

On the Reliability of Systems with Warm Redundancy and Unreliable Switching Equipment

Abstract: The reliability of two contrary reconfiguration circuitries for computer systems with warm redundancy are compared by using renewal-theoretical methods. Buricius et al. demonstrated in their summarizing paper [BUR] the sensitiveness of dynamic replacement computers to their coverage, i.e. the conditional probability that the system recovers after a failure occured. In our model the procedure of failure recognization, -location, repair, roll back and restart,for short the process of recovery will be thought of successfully switching in a spare unit whenever the activ unit fails. A similar model has been examined in [ARN]. Amongst others [REN] emphasizes the importance of the coverage-factor c for the systems reliability. In our model all life times are assumed to be distributed exponentially. The switch is operating independently of the state of the rest of the system (for a discussion of this assumption compare [REN]). The two reconfiguration structures to be discussed are shown below: (S stands for (the same) realization of the switch.) Open image in new window

Organizing Space Shuttle parametric data for maintainability

Abstract: A model of organization and management of Space Shuttle data is proposed. Shuttle avionics software is parametrically altered by a reconfiguration process for each flight. As the flight rate approaches an operational level, current methods of data management would become increasingly complex. An alternative method is introduced, using modularized standard data, and its implications for data collection, integration, validation, and reconfiguration processes are explored. Information modules are cataloged for later use, and may be combined in several levels for maintenance. For each flight, information modules can then be selected from the catalog at a high level. These concepts take advantage of the reusability of Space Shuttle information to reduce the cost of reconfiguration as flight experience increases.