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Showing papers on "Control reconfiguration published in 1998"


Journal ArticleDOI
TL;DR: An overview of the holonic reference architecture for manufacturing systems as developed at PMA-KULeuven, which shows PROSA shows to cover aspects of both hierarchical as well as heterarchical control approaches.

1,408 citations


Book ChapterDOI
28 Mar 1998
TL;DR: This paper argues that it is possible and valuable to provide a modeling approach that accounts for the interactions between architectural reconfiguration and non-reconfiguration system functionality, while maintaining a separation of concerns between these two aspects of a system.
Abstract: A critical issue for complex component-based systems design is the modeling and analysis of architecture. One of the complicating factors in developing architectural models is accounting for systems whose architecture changes dynamically (during run time). This is because dynamic changes to architectural structure may interact in subtle ways with on-going computations of the system. In this paper we argue that it is possible and valuable to provide a modeling approach that accounts for the interactions between architectural reconfiguration and non-reconfiguration system functionality, while maintaining a separation of concerns between these two aspects of a system. The key to the approach is to use a uniform notation and semantic base for both reconfiguration and steady-state behavior, while at the same time providing syntactic separation between the two. As we will show, this permits us to view the architecture in terms of a set of possible architectural snapshots, each with its own steady-state behavior. Transitions between these snapshots are accounted for by special reconfiguration-triggering events.

427 citations


Proceedings ArticleDOI
16 May 1998
TL;DR: A prototype unit is designed and built to examine the feasibility of the 3-D self-reconfigurable concept, the design of the unit, method of reconfiguration, hardware implementation, and results of preliminary experiments are shown.
Abstract: A three-dimensional, self-reconfigurable structure is proposed. The structure is a fully distributed system composed of many identical 3-D units. Each unit has functions of changing local connection, information processing, and communication among neighborhood units. Groups of units cooperate to change their connection so that the shape of the whole solid structure transforms into an arbitrary shape. Also, the structure can repair itself by rejecting faulty units, replacing them with spare units. This kind of self-maintainability is essential to structure's longevity in hazardous or remote environments such as space or deep sea where human operators cannot approach. We have designed and built a prototype unit to examine the feasibility of the 3-D self-reconfigurable concept. The design of the unit, method of reconfiguration, hardware implementation, and results of preliminary experiments are shown. In the last part of the paper, distributed software for self-reconfiguration is discussed.

259 citations


Proceedings ArticleDOI
15 Apr 1998
TL;DR: Sanders, A Lockheed Martin Company, is developing the enabling technology to exploit dynamic reconfiguration of field programmable gate arrays, capable of storing four configurations on-chip and switching between them on a clock cycle basis.
Abstract: Dynamic reconfiguration of field programmable gate arrays (FPGAs) has recently emerged as the next step in reconfigurable computing. Sanders, A Lockheed Martin Company, is developing the enabling technology to exploit dynamic reconfiguration. The device being developed is capable of storing four configurations on-chip and switching between them on a clock cycle basis. Configurations can be loaded while other contexts are active. A powerful cross-context data sharing mechanism has been implemented. The current status of this work and future work are described.

212 citations


Patent
26 Jan 1998
TL;DR: In this article, a method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities and hardware functionalities.
Abstract: A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

195 citations


Journal ArticleDOI
TL;DR: In this article, a new approach to solve the distribution feeder reconfiguration problem for loss reduction and service restoration is presented, where Meshed networks were considered instead of the radial topology by closing all the tie switches.
Abstract: This paper presents a new approach to solve the distribution feeder reconfiguration problem for loss reduction and service restoration. By using the proposed algorithm, a more efficient network configuration can be obtained to reduce loss. Three switching indices were defined in this paper. Branch voltage-drops and line constants were used with all the electrical constraints. Meshed networks were considered instead of the radial topology by closing all the tie switches. By considering only the largest switching index in each loop, this algorithm can reduce the number of feasible states drastically. The switching index can also be used for service restoration. Many tests have been run to show its effectiveness.

195 citations


Proceedings ArticleDOI
01 Mar 1998
TL;DR: This paper proposes one technique for significantly reducing the reconfiguration latency: the prefetching of configurations, and proposes an algorithm for automatically adding prefetch operations into reconfigurable applications.
Abstract: Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the power of reconfigurable systems, it is important to develop hardware and software systems to reduce or eliminate this delay. In this paper we propose one technique for significantly reducing the reconfiguration latency: the prefetching of configurations. By loading a configuration into the reconfigurable logic in advance of when it is needed, we can overlap the reconfiguration with useful computation. We demonstrate the power of this technique, and propose an algorithm for automatically adding prefetch operations into reconfigurable applications. This results in a significant decrease in the reconfiguration overhead for these applications.

181 citations


Patent
Steven A. Guccione1
07 Aug 1998
TL;DR: In this paper, the authors present a software environment for reconfigurable coprocessor applications that includes a standard high level language compiler (i.e. Java) and a set of libraries.
Abstract: A method of designing FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.

178 citations


Journal ArticleDOI
TL;DR: A new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's) to provide redundant backup for several types of components.
Abstract: Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight We have developed a new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's) The physical design is partitioned into a set of tiles In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile Unlike application specific integrated circuit (ASIC) and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead

171 citations


Journal ArticleDOI
TL;DR: In this article, the authors describe the philosophy and the implementation of a preventive control algorithm for application in power system dynamic security assessment, which consists of an optimization procedure where: the objective function takes into account economic costs; inequality constraints confine the trajectory of the system in a practical domain of the state space; and equality constraints derive from the discretization of the differential-algebraic equations of the power system sparse representation.
Abstract: This paper describes the philosophy and the implementation of a preventive control algorithm for application in power system dynamic security assessment. The methodology consists of an optimization procedure where: the objective function takes into account economic costs; inequality constraints confine the trajectory of the system in a practical domain of the state space; and equality constraints derive from the discretization of the differential-algebraic equations of the power system sparse representation. The algorithm has been implemented to reschedule the power system generation in order to guarantee transient stability. The feasibility of the approach is shown through computer simulation tests on a realistic sized test network.

165 citations


Journal ArticleDOI
TL;DR: In this article, a framework for the analyses of supply chain reconfiguration patterns in the context of internationalization strategy is introduced and used in eight case studies, and different postponement applications have been found, suggesting that the existing framework for customization in supply chains needs extension.
Abstract: It is expected that, as the next step in the development of distribution channels, companies will decentralize their final manufacturing into their distribution centers. It has also been suggested that companies are increasingly beginning to customize products based on customer orders. Both the repositioning of final manufacturing into the distribution channel and the move towards customization‐on‐order are related to the implementation of postponed manufacturing. A framework for the analyses of supply chain reconfiguration patterns in the context of internationalization strategy is introduced and used in eight case studies. Results suggest that the implementation of postponed manufacturing require not only the reconfiguration of the logistics systems, but also that of other operations in the supply chain, thus creating a cross‐functional effect. In contrast to the literature different paths are found which are viable for structuring the reconfiguration process. Finally, different postponement applications have been found, suggesting that the existing framework for customization in supply chains needs extension.

Proceedings ArticleDOI
21 Jun 1998
TL;DR: The design of the corresponding adaptive laws based on Lyapunov analysis allow us to prove global stability of the overall scheme in the presence of multiple actuator failures.
Abstract: The paper describes the design of an automatic control reconfiguration scheme for accommodation of actuator failures in a class of plants where the number of control inputs is larger than the number of controlled outputs. One of the main features of the proposed scheme is that the control reconfiguration is achieved automatically based only on the response of the overall system. The method is developed for the case when one or more actuators freeze in a certain position and do not respond to subsequent commands. We assumed that the information about the failure is not available to the controller. To solve this problem, a control law with adjustable parameters is introduced, and, using a convenient parametrization of the overall system, the resulting error model is expressed in a somewhat modified form as compared to those arising in standard adaptive control. The design of the corresponding adaptive laws based on Lyapunov analysis allow us to prove global stability of the overall scheme in the presence of multiple actuator failures.

Patent
Vincent T. Bocchino1
19 Feb 1998
TL;DR: In this paper, a technique for configuring programmable integrated circuits is presented, which involves preconditioning or predefining the outputs and I/Os of a programmable IC before the device is programmed or reconfigured.
Abstract: A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149.1 boundary scan architecture standard. Standard IEEE 1149.1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.

Proceedings ArticleDOI
16 May 1998
TL;DR: A novel concept of self-organizing collective robots with morphogenesis in a vertical plane is presented, potentially applicable to autonomous mobile robots and the algorithms proposed can locally generate specific global formations of robots, with minimum interactions between neighboring robots.
Abstract: This paper presents a novel concept of self-organizing collective robots with morphogenesis in a vertical plane. It is potentially applicable to autonomous mobile robots. For physical reconfiguration of a swarm of robots against gravity, new types of mechanisms and control strategies are proposed and demonstrated. Prototype robots have been fabricated in order to confirm the basic feasibility of the mechanisms. Each robot is composed of a body and a pair of arms. The body can be regarded as a cube with edge length of 90 mm, and is equipped with permanent magnets for bonding with another robot. The arms change the bonding configuration by rotating and sliding motions. As for the control strategies, we proposed the algorithms which can locally generate specific global formations of robots, with minimum interactions between neighboring robots. The overall scheme is similar to cellular automata. The control algorithms proposed have been tested by simulations.

Proceedings ArticleDOI
15 Apr 1998
TL;DR: An algorithm is developed, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration, resulting in an overall reduction of almost 4 in total bandwidth required for reconfigurations.
Abstract: One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system This overhead limits the speedups possible in this exciting new paradigm In this paper we explore one technique for reducing this overhead: the compression of configuration datastreams We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration This results in an overall reduction of almost 4 in total bandwidth required for reconfiguration

Journal ArticleDOI
TL;DR: Compared to other techniques for fault tolerance in FPGAs, these methods are shown to provide significantly greater yield improvement, and a 35 percent non-FT chip yield for a 16/spl times/16 FPGA is more than doubled.
Abstract: The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational faults. Thus, there is a critical need for fault tolerance and reconfiguration techniques for FPGAs to increase chip yields (with factory reconfiguration) and/or system reliability (with field reconfiguration). We first propose techniques utilizing the principle of node-covering to tolerate logic or cell faults in SRAM-based FPGAs. A routing discipline is developed that allows each cell to cover-to be able to replace-its neighbor in a row. Techniques are also proposed for tolerating wiring faults by means of replacement with spare portions. The replaceable portions can be individual segments, or else sets of segments, called "grids". Fault detection in the FPGAs is accomplished by separate testing, either at the factory or by the user. If reconfiguration around faulty cells and wiring is performed at the factory (with laser-burned fuses, for example), it is completely transparent to the user. In other words, user configuration data loaded into the SRAM remains the same, independent of whether the chip is detect-free or whether it has been reconfigured around defective cells or wiring-a major advantage for hardware vendors who design and sell FPGA-based logic (e.g., glue logic in microcontrollers, video cards, DSP cards) in production-scale quantities. Compared to other techniques for fault tolerance in FPGAs, our methods are shown to provide significantly greater yield improvement, and a 35 percent non-FT chip yield for a 16/spl times/16 FPGA is more than doubled.

Proceedings ArticleDOI
04 Mar 1998
TL;DR: The novelty of the algorithm is that it passivates the links affected by the reconfiguration, which causes the node activities that use them to block but does not result in blocking the entire node.
Abstract: Providing software qualities such as availability, adaptability and maintainability to long-running distributed applications forms a major challenge for the configuration management of a software system. Modifications of a system's structure are expected to happen on-the-fly, to cause minimum execution disruption and to be effected in a way that preserves a consistent state of the participating entities. This paper presents a novel algorithm for performing consistent dynamic reconfiguration of CORBA applications, where consistency refers to RPC integrity. The novelty of the algorithm is that it passivates the links affected by the reconfiguration, which causes the node activities that use them to block but does not result in blocking the entire node. The consequent execution disruption is minimal, a fact that is practically verified by a performance evaluation done in a number of different reconfiguration scenarios.

Journal ArticleDOI
TL;DR: An integer programming model is developed to minimize material handling and machine costs as well as cell reconfiguration cost for a planning horizon of multiple time periods and decomposed subproblems can be solved with less computational effort.
Abstract: In a dynamic manufacturing environment, manufacturing cell configurations based on current part mix and production process may need to be revised once the part mix or the production process has changed. However, machine and equipment moving costs make frequent reconfiguration uneconomical and sometimes impossible. Designing a sustainable cellular manufacturing system in a dynamic environment is studied in this paper. An integer programming model is developed to minimize material handling and machine costs as well as cell reconfiguration cost for a planning horizon of multiple time periods. Solving this integer programming problem is NP-complete. A decomposition approach is developed so that the decomposed subproblems can be solved with less computational effort. Dynamic programming is then employed to find a solution of the original problem. Numerical examples are presented to illustrate the model and the solution technique developed in this paper.

Proceedings ArticleDOI
01 Mar 1998
TL;DR: This paper describes the benefits of hardware virtualization, and shows how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams to create PipeRench, an architecture that supports robust compilation and provides forward compatibility.
Abstract: While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2.

Journal ArticleDOI
TL;DR: The New Millennium Remote Agent architecture supports challenging requirements of the autonomous spacecraft domain not usually addressed in mobile robot architectures, including highly reliable autonomous operations over extended time periods in the presence of tight resource constraints, hard deadlines, limited observability, and concurrent activity.
Abstract: This paper describes the New Millennium Remote Agent (NMRA) architecture for autonomous spacecraft control systems. The architecture supports challenging requirements of the autonomous spacecraft domain not usually addressed in mobile robot architectures, including highly reliable autonomous operations over extended time periods in the presence of tight resource constraints, hard deadlines, limited observability, and concurrent activity. A hybrid architecture, NMRA integrates traditional real-time monitoring and control with heterogeneous components for constraint-based planning and scheduling, robust multi-threaded execution, and model-based diagnosis and reconfiguration. Novel features of this integrated architecture include support for robust closed-loop generation and execution of concurrent temporal plans and a hybrid procedural/deductive executive. We implemented a prototype autonomous spacecraft agent within the architecture and successfully demonstrated the prototype in the context of a challenging autonomous mission scenario on a simulated spacecraft. As a result of this success, the integrated architecture has been selected to fly as an autonomy experiment on Deep Space One (DS-1), the first flight of NASA‘s New Millennium Program (NMP), which will launch in 1998. It will be the first AI system to autonomously control an actual spacecraft.

Patent
27 May 1998
TL;DR: A reconfigurable manufacturing system (RMS) as discussed by the authors is a manufacturing system that can be easily adapted to fabrication of new products of the same product family by reconfiguration.
Abstract: A reconfigurable manufacturing system (RMS) having an adjustable structure is designed based upon market demand and can be readily changed from a first desired production capacity to a second desired production capacity to manufacture a desired amount of products from a family of products The RMS includes a plurality of workstations with reconfigurable machines and computerized numerically controlled (CNC) machines, a control system including a plurality of reconfigurable controllers, as well as a reconfigurable material handling system The reconfigurable machines may be reconfigurable machine tools having reconfigurable hardware that enables conversion of the machines by, for example, relocating their spindle units The RMS production capacity is quickly adjusted to market fluctuations in product demand The RMS functionality is easily adapted to fabrication of new products of the same product family The RMS possesses certain key characteristics (ie, modularity, integrability, customization, convertability, and diagnosability) that are needed for rapid and cost-effective reconfiguration A methodology for the design of an RMS, and a complementary methodology for changing the production capacity including reconfiguration and ramp-up of the RMS are also provided

Proceedings ArticleDOI
16 Dec 1998
TL;DR: It is shown that the key element is the design of sufficiently robust individual controllers for each of the damage conditions using a combination of inverse dynamics and output error feedback control laws.
Abstract: We consider a problem of designing a reconfigurable control strategy that achieves acceptable flight performance in the presence of wing battle damage for a tailless advanced fighter aircraft (TAFA). This is a complex practical problem since wing damage results in abrupt variation in the aircraft dynamics. Hence fast and accurate control reconfiguration is vital for assuring aircraft survivability. Our suggested reconfigurable controller is based on the concept of multiple models, switching, and tuning. The overall control system consists of multiple parallel identification models, describing different percentages of wing damage, and corresponding controllers. Based on a suitably chosen switching mechanism, the system quickly finds the model that is closest to the current damage mode, and switches to the corresponding controller achieving excellent overall performance. In addition, the boundedness of the signals in the system is guaranteed if the switching interval is chosen to be sufficiently small. It is shown that the key element is the design of sufficiently robust individual controllers for each of the damage conditions. This has been accomplished using a combination of inverse dynamics and output error feedback control laws. The properties of the overall system are illustrated through simulations using linearized TAFA models provided by Boeing. Simulation results have demonstrated the potential of the multiple model-based approach to solve complex practical reconfigurable control design problems.

Journal ArticleDOI
TL;DR: A functional density metric is introduced that balances the advantages of RTR against its associated reconfigurability costs and is used to justify run-time reconfiguration against other more conventional approaches.
Abstract: The ability to provide flexibility and allow fine-grain circuit specialization make field programmable gate arrays (FPGA's) ideal candidates for computing elements within application-specific architectures. The benefits of gate-level specialization and reconfigurability can be extended by reconfiguring circuit resources at run-time. This technique, termed run-time reconfiguration (RTR), allows the exploitation of dynamic conditions or temporal locality within application-specific problems. For several applications, this technique has been shown to reduce the hardware resources required for computation. The use of this technique on conventional FPGA's, however, requires additional time for circuit reconfiguration. A functional density metric is introduced that balances the advantages of RTR against its associated reconfiguration costs. This metric is used to justify run-time reconfiguration against other more conventional approaches. Several run-time reconfigured applications are presented and analyzed using this approach.

Journal ArticleDOI
TL;DR: This paper addresses the question of whether UNITY, a state-based formalism with a foundation in temporal logic, can be extended to address concurrent, mobile systems and examines some new abstractions for communication among mobile components that express reconfiguration and disconnection and which can be composed in a modular fashion.
Abstract: Recent advances in wireless networking technology and the increasing demand for ubiquitous, mobile connectivity demonstrate the importance of providing reliable systems for managing the reconfiguration and disconnection of components. The design of such systems requires tools and techniques appropriate to the task. Many formal models of computation, including UNITY, are not adequate for expressing reconfiguration and disconnection and are, therefore, inappropriate vehicles for investigating the impact of mobility on the construction of modular and composable systems. Algebraic formalisms such as the /spl pi/-calculus have been proposed for modeling mobility. This paper addresses the question of whether UNITY, a state-based formalism with a foundation in temporal logic, can be extended to address concurrent, mobile systems. In the process, we examine some new abstractions for communication among mobile components that express reconfiguration and disconnection and which can be composed in a modular fashion.

Proceedings ArticleDOI
15 Apr 1998
TL;DR: A method that automates a key step in producing run-time reconfiguring designs: the identification and mapping of reconfigurable regions by matching two successive circuit configurations to locate the components common to them.
Abstract: This paper describes a method that automates a key step in producing run-time reconfigurable designs: the identification and mapping of reconfigurable regions. In this method, two successive circuit configurations are matched to locate the components common to them, so that reconfiguration time can be minimized. The circuit configurations are represented as a weighted bipartite graph, to which an efficient matching algorithm is applied. Our method, which supports hierarchical and library-based design, is device-independent and has been tested using Xilinx 6200 FPGAs. A number of examples in arithmetic, pattern matching and image processing are selected to illustrate our approach.

Proceedings ArticleDOI
16 Dec 1998
TL;DR: The model predictive control strategy is used as a basic control law within the framework of multiple models, switching and tuning to design a reconfigurable flight control system that can explicitly take into account hard constraints on control inputs, and achieve acceptable flight performance in the presence of control effector freezing.
Abstract: The model predictive control (MPC) strategy is used as a basic control law within the framework of multiple models, switching and tuning to design a reconfigurable flight control system. The controller described can explicitly take into account hard constraints on control inputs, and achieve acceptable flight performance in the presence of control effector freezing. To arrive at an effective reconfigurable control design, a new parametrization of the aircraft model in the presence of control effector freezing is suggested. It turned out that such a parametrization is well suited for use within the MPC framework. The overall multiple model predictive control scheme quickly identifies the nature and time instant of the failure, and carries out automatic reconfiguration of the control law achieving acceptable flight performance. The properties of our reconfigurable controller are evaluated through simulations of an F/A-18A aircraft carrier landing manoeuvre in the presence of critical control effector failures.

Journal ArticleDOI
TL;DR: In this paper, the authors developed techniques to increase survivability, eliminate human mistakes, make intelligent reconfiguration decisions more quickly, reduce the manpower required to perform the functions and provide optimal electric power service through the surviving system.
Abstract: The electric power systems in today's US Navy ships supply energy to sophisticated systems for weapons, communications, navigation and operation. To maintain the availability of energy to the connected loads that keep all systems and equipment operational, the electric systems utilize fuses, circuit breakers and protective relays to interrupt the smallest portion of the system under any abnormal condition. New techniques are being developed that make use of advanced monitoring and control, automated failure location and automated intelligent system reconfiguration and restoration. The goal is to increase survivability, eliminate human mistakes, make intelligent reconfiguration decisions more quickly, reduce the manpower required to perform the functions and provide optimal electric power service through the surviving system. With fewer personnel being available on ships in the future, the presence of such a system will become essential for maintaining optimal electric power service.

Proceedings ArticleDOI
01 Nov 1998
TL;DR: Experimental results indicate that using dynamically reconfigured FPGAs in distributed real-time embedded systems has the potential to reduce their price and allow the synthesis of architectures which meet system specifications that would otherwise be infeasible.
Abstract: Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this feature is seldom exploited. Recent improvements in the flexibility and reconfiguration speed of FPGAs have made it practical to reconfigure them dynamically, reducing the amount of hardware required in an embedded system. We have developed a system, called CORDS, which synthesizes multi-rate, real-time, periodic distributed embedded systems containing dynamically reconfigurable FPGAs. Executing different tasks on the same FPGA requires that potentially time-consuming reconfiguration be carried out between tasks. CORDS uses a novel preemptive, dynamic priority, multi-rate scheduling algorithm to deal with this problem. To the best of our knowledge, dynamically reconfigured FPGAs have not previously been used in hardware-software co-synthesis of embedded systems. Experimental results indicate that using dynamically reconfigured FPGAs in distributed real-time embedded systems has the potential to reduce their price and allow the synthesis of architectures which meet system specifications that would otherwise be infeasible.

Proceedings ArticleDOI
01 Mar 1998
TL;DR: A fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight and capitalize on the unique reconfiguration capabilities of FPGAs to replace the affected tile with a functionally equivalent tile that does not rely on the faulty component.
Abstract: While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical design into a set of tiles. In response to a component failure, we capitalize on the unique reconfiguration capabilities of FPGAs and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of realiability with low timing and hardware overhead.

Journal ArticleDOI
TL;DR: A technique for on-line built-in self-testing of bus-based field programmable gate arrays (FPGAs) without using special-purpose hardware, hardware external to the device, and without interrupting system operation is introduced.
Abstract: We introduce a technique for on-line built-in self-testing (BIST) of bus-based field programmable gate arrays (FPGAs). This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system.