Showing papers on "Control reconfiguration published in 2003"

PACT XPP—A Self-Reconfigurable Data Processing Architecture

Abstract: The eXtreme Processing Platform (XPPTM) is a new runtime-reconfigurable data processing architecture. It is based on a hierarchical array of coarsegrain, adaptive computing elements, and a packet-oriented communication network. The strength of the XPPTM technology originates from the combination of array processing with unique, powerful run-time reconfiguration mechanisms. Parts of the array can be configured rapidly in parallel while neighboring computing elements are processing data. Reconfiguration is triggered externally or even by special event signals originating within the array, enabling self-reconfiguring designs. The XPPTM architecture is designed to support different types of parallelism: pipelining, instruction level, data flow, and task level parallelism. Therefore this technology is well suited for applications in multimedia, telecommunications, simulation, signal processing (DSP), graphics, and similar stream-based application domains. The anticipated peak performance of the first commercial device running at 150 MHz is estimated to be 57.6 GigaOps/sec, with a peak I/O bandwidth of several GByte/sec. Simulated applications achieve up to 43.5 GigaOps/sec (32-bit fixed point).

Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

Abstract: A Multiple Clock Domain (MCD) processor addresses the challenges of clock distribution and power dissipation by dividing a chip into several (coarse-grained) clock domains, allowing frequency and voltage to be reduced in domains that are not currently on the application's critical path. Given a reconfiguration mechanism capable of choosing appropriate times and values for voltage/frequency scaling, an MCD processor has the potential to achieve significant energy savings with low performance degradation.Early work on MCD processors evaluated the potential for energy savings by manually inserting reconfiguration instructions into applications, or by employing an oracle driven by off-line analysis of (identical) prior program runs. Subsequent work developed a hardware-based on-line mechanism that averages 75--85% of the energy-delay improvement achieved via off-line analysis.In this paper we consider the automatic insertion of reconfiguration instructions into applications, using profile-driven binary rewriting. Profile-based reconfiguration introduces the need for "training runs" prior to production use of a given application, but avoids the hardware complexity of on-line reconfiguration. It also has the potential to yield significantly greater energy savings. Experimental results (training on small data sets and then running on larger, alternative data sets) indicate that the profile-driven approach is more stable than hardware-based reconfiguration, and yields virtually all of the energy-delay improvement achieved via off-line analysis.

Dynamic cluster reconfiguration for power and performance

Abstract: In this chapter we address power conservation for clusters of workstations or PCs. Our approach is to develop systems that dynamically turn cluster nodes on - to be able to handle the load imposed on the system efficiently - and off - to save power under lighter load. The key component of our systems is an algorithm that makes cluster reconfiguration decisions by considering the total load imposed on the system and the power and performance implications of changing the current configuration. The algorithm is implemented in two common cluster-based systems: a network server and an operating system for clustered cycle servers. Our experimental results are very favorable, showing that our systems conserve both power and energy in comparison to traditional systems.

A Self-reconfiguring Platform

Abstract: A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor This platform has been implemented on Xilinx Virtex IItm and Virtex II Protm devices The platform’s hardware architecture has been designed to be lightweight Two APIs (Application Program Interface) are described which abstract the low level configuration interface The Xilinx Partial Reconfiguration Toolkit (XPART), the higher level of the two APIs, provides methods for reading and modifying select FPGA resources It also provides support for relocatable partial bitstreams The presented self-reconfiguring platform enables embedded applications to take advantage of dynamic partial reconfiguration without requiring external circuitry

A design strategy for reconfigurable manufacturing systems (RMSs)using analytical hierarchical process (AHP): a case study

Abstract: This paper presents Reconfigurable Manufacturing System (RMS) characteristics through comparison with conventional manufacturing systems in order to address a design strategy towards a RMS. The strategy is considered as a part of a RMS design loop to achieve a reconfigurable strategy over its implementation period. As another part of the design loop, a reconfiguration link between market and manufacturing is presented in order to group products into families (reconfiguring products) and then assign them to the required manufacturing processes over configuration stages. In particular, the Analytical Hierarchical Process (AHP) is employed for structuring the decision making process for the selection of a manufacturing system among feasible alternatives based on the RMS study. Manufacturing responsiveness is considered as the ability of using existing resources to reflect new environmental and technological changes quickly. The AHP model highlights manufacturing responsiveness as a new economic objective alo...

Fast online task placement on FPGAs: free space partitioning and 2D-hashing

Abstract: Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs raises a number of questions on the management of the reconfigurable resource which leads to the concept of a reconfigurable operating system. A major aspect of such an operating system is task placement. Online placement methods are required that achieve a high placement quality and lead to efficient implementations. This paper presents placement methods that rely on efficient algorithms for the partitioning of the reconfigurable resource and a hash matrix data structure to maintain the free space. Given n as the number of currently placed tasks, previously known placers find a feasible location in O(n) time. Our approach is able to find a feasible location in constant time. Additionally, simulations show that our methods improve the placement quality by up to 70%.

System Support for Online Reconfiguration

Abstract: Online reconfiguration provides a way to extend and replace active operating system components. This provides administrators, developers, applications, and the system itself with a way to update code, adapt to changing workloads, pinpoint performance problems, and perform a variety of other tasks while the system is running. With generic support for interposition and hot-swapping, a system allows active components to be wrapped with additional functionality or replaced with different implementations that have the same interfaces. This paper describes support for online reconfiguration in the K42 operating system and our initial experiences using it. It describes four base capabilities that are combined to implement generic support for interposition and hot-swapping. As examples of its utility, the paper describes some performance enhancements that have been achieved with K42’s online reconfiguration mechanisms including adaptive algorithms, common case optimizations, and workload specific specializations.

Real-Time Optimal Trajectory Generation for Constrained Dynamical Systems

Abstract: With the advent of powerful computing and efficient computational algorithms, real-time solutions to constrained optimal control problems are nearing a reality. In this thesis, we develop a computationally efficient Nonlinear Trajectory Generation (NTG) algorithm and describe its software implementation to solve, in real-time, nonlinear optimal trajectory generation problems for constrained systems. NTG is a nonlinear trajectory generation software package that combines nonlinear control theory, B-spline basis functions, and nonlinear programming. We compare NTG with other numerical optimal control problem solution techniques, such as direct collocation, shooting, adjoints, and differential inclusions. We demonstrate the performance of NTG on the Caltech Ducted Fan testbed. Aggressive, constrained optimal control problems are solved in real-time for hover-to-hover, forward flight, and terrain avoidance test cases. Real-time trajectory generation results are shown for both the two-degree of freedom and receding horizon control designs. Further experimental demonstration is provided with the station-keeping, reconfiguration, and deconfiguration of micro-satellite formation with complex nonlinear constraints. Successful application of NTG in these cases demonstrates reliable real-time trajectory generation, even for highly nonlinear and non-convex systems. The results are among the first to apply receding horizon control techniques for agile flight in an experimental setting, using representative dynamics and computation.

A Lightweight Approach for Embedded Reconfiguration of FPGAs

Abstract: This paper presents a lightweight approach for embedded reconfiguration of Xilinx Virtex II/spl trade/ series FPGAs. A hardware and software infrastructure is reported that enables an FPGA to dynamically reconfigure itself under the control of a soft microprocessor core that is instantiated on the same array. The system provides a highly integrated, lightweight approach to dynamic reconfiguration for embedded systems. It combines the benefits of intelligent control, fast reconfiguration and small overhead.

Kinesthetics eXtreme: an external infrastructure for monitoring distributed legacy systems

Abstract: Autonomic computing - self-configuring, self-healing, self-optimizing applications, systems and networks - is widely believed to be a promising solution to ever-increasing system complexity and the spiraling costs of human system management as systems scale to global proportions. Most results to date, however, suggest ways to architect new software constructed from the ground up as autonomic systems, whereas in the real world organizations continue to use stovepipe legacy systems and/or build ''systems of systems'' that draw from a gamut of new and legacy components involving disparate technologies from numerous vendors. Our goal is to retrofit autonomic computing onto such systems, externally, without any need to understand or modify the code, and in many cases even when it is impossible to recompile. We present a meta-architecture implemented as active middleware infrastructure to explicitly add autonomic services via an attached feedback loop that provides continual monitoring and, as needed, reconfiguration and/or repair. Our lightweight design and separation of concerns enables easy adoption of individual components, as well as the full infrastructure, for use with a large variety of legacy, new systems, and systems of systems. We summarize several experiments spanning multiple domains.

Reconfiguration of a programmable logic device using internal control

Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Dynamically managing the communication-parallelism trade-off in future clustered processors

Abstract: Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, thereby allowing more aggressive use of instruction-level parallelism (ILP), the inter-cluster communication increases as data values get spread across a wider area. As a result of the emergence of this trade-off between communication and parallelism, a subset of the total on-chip clusters is optimal for performance. To match the hardware to the application's needs, we use a robust algorithm to dynamically tune the clustered architecture. The algorithm, which is based on program metrics gathered at periodic intervals, achieves an 11% performance improvement on average over the best statically defined architecture. We also show that the use of additional hardware and reconfiguration at basic block boundaries can achieve average improvements of 15%. Our results demonstrate that reconfiguration provides an effective solution to the communication and parallelism trade-off inherent in the communication-bound processors of the future.

Fault diagnosis and reconfiguration in flight control systems

Abstract: The problem of fault diagnosis and reconfigurable control is a new and actually developing field of science and engineering. The subject becomes more interesting since there is an increasing demand for the navigation and control systems of aerospace vehicles, automated actuators etc. to be more safe and reliable. Nowadays, the problems of fault detection and isolation and reconfigurable control attract the attention the scientists in the world. The subject is emphasized in the recent international congresses such as IF AC World Congresses (San Francisco-1996, Beijing-1999, and Barcelona-2002) and lMEKO World Congresses (Tampere-1997, Osaka-1999, Vienna-2000), and also in the international conferences on fault diagnosis such as SAFEPROCESS Conferences (Hull-1997, Budapest-2000). The presented methods in the book are based on linear and nonlinear dynamic mathematical models of the systems. Technical objects and systems stated by these models are very large, and include various control systems, actuators, sensors, computer systems, communication systems, and mechanical, hydraulic, pneumatic, electrical and electronic devices. The analytical fault diagnosis techniques of these objects have been developed for several decades. Many of those techniques are based on the use of the results of modem control theory. This is natural, because it is known that fault diagnosis process in control systems is considered as a part of general control process. xxii In organization of fault diagnosis of control systems, the use of the concepts and methods of modem control theory including concepts of state space, modeling, controllability, observability, estimation, identification, and filtering is very efficient.

Virtual reconfigurable circuits for real-world applications of evolvable hardware

Abstract: The paper introduces a new method for the design of real-world applications of evolvable hardware using common FPGAs (Field Programmable Gate Arrays). In order to avoid "reconfiguration problems" of current FPGAs a new virtual reconfigurable circuit, whose granularity and configuration schema exactly fit to requirements of a given application, is designed on the top of an ordinary FPGA. As an example, a virtual reconfigurable circuit is constructed to speed up the software model, which was utilized for the evolutionary design of image operators.

System and method for lighting control network recovery from master failure

Abstract: The present invention provides a master-slave architecture for a radio frequency RF networked lighting control system having all slave elements (ballasts) configured as backups for a network master control unit. In the system and method of the present invention a slave element can become the network master network unit without reconfiguring the network and without any human intervention. Similarly, both a master and one or more slave elements may recover from a temporary outage without necessitating reconfiguration of the network and without any human intervention.

Reconfigurable Flight Control System Design Using Direct Adaptive Method

Abstract: A reconfigurable flight control system provides better survivability through the automatic reconfiguration of control system when faults occur during flight. The adaptive control method has been effectively applied to the reconfigurable flight control system design. However, reconfigurable flight control systems based on the indirect adaptive control method require persistent input excitation and smooth input-output data. To deal with the persistent input excitation problem and to obtain smooth control input, the system identification algorithm in reconfiguration flight control systems usually imposes some constraints on past input-output data, which may deteriorate the reconfiguration performance. Thus, a new reconfigurable flight control system based on the direct adaptive method is proposed to achieve better reconfiguration performance without the system identification process. The proposed control method uses a model following controller with direct adaptive update rules. To control the inner-loop states and the outer-loop states of the flight system simultaneously,the timescale separation principle is applied. The reconfiguration performance of the proposed control method is evaluated through numerical simulations using a six-degree-of-freedom nonlinear aircraft model.

Efficient content-based event dispatching in the presence of topological reconfiguration

Abstract: Distributed content-based publish-subscribe middleware provides the decoupling, flexibility, expressiveness, and scalability required by highly dynamic distributed applications, e.g., mobile ones. Nevertheless, the available systems exploiting a distributed event dispatcher are unable to rearrange dynamically their behavior to adapt to changes in the topology of the dispatching infrastructure. In this work, we first define a strawman solution based on ideas proposed (but never precisely characterized) in existing work. We then analyze this solution and achieve a deeper understanding of how the event dispatching information is reconfigured. Based on this analysis, we modify the strawman approach to reduce its overhead. Simulations show that the reduction is significant (up to 50%), and yet the algorithm is resilient to concurrent reconfigurations.

Method, system, and program for handling a failover to a remote storage location

Abstract: Provided are a method, program, and system for managing data. A mirror policy is processed indicating volumes in a first storage system to mirror to volumes in a second storage system and volumes in the second storage system to mirror to volumes in a third storage system, wherein the third storage system is at a first geographical location remote with respect to a second geo­graphical location including the first and second storage systems. A failure is detected of the first and second storage systems at the first geographical location. Automatic reconfiguration is made to network resources directing I/O requests to volumes in the first storage system to direct I/O requests to volumes in the third storage system. A failure of the first storage system and the availability of the second storage system is detected and, in response, network resources are re­configured to direct I/O requests to volumes in the first storage system to volumes in the second storage system in response to detecting the failure of the first storage system and the availability of the second storage system. Updates to the second storage system are copied to the third storage system after reconfiguring network resources to direct I/O requests to volumes in the first storage system to volumes in the second storage system.

SRS: A framework for developing malleable and migratable parallel applications for distributed systems

Abstract: The ability to produce malleable parallel applications that can be stopped and reconfigured during the execution can offer attractive benefits for both the system and the applications. The reconfiguration can be in terms of varying the parallelism for the applications, changing the data distributions during the executions or dynamically changing the software components involved in the application execution. In distributed and Grid computing systems, migration and reconfiguration of such malleable applications across distributed heterogeneous sites which do not share common file systems provides flexibility for scheduling and resource management in such distributed environments. The present reconfiguration systems do not support migration of parallel applications to distributed locations. In this paper, we discuss a framework for developing malleable and migratable MPI message-passing parallel applications for distributed systems. The framework includes a user-level checkpointing library called SRS and a runtime support system that manages the checkpointed data for distribution to distributed locations. Our experiments and results indicate that the parallel applications, with instrumentation to SRS library, were able to achieve reconfigurability incurring about 15-35% overhead.

A reconfigurable shared scan-in architecture

Abstract: In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitations

Abstract: The power consumption of reconfigurable systems has become a fundamental aspect in designing applications. Especially for mobile systems with a limited power supply, it is necessary to identify and optimize the power loss. Moreover, it is essential to evaluate during application development time exact power trade-offs, especially including the consideration of the dynamic reconfiguration phases of corresponding devices, e.g. the Virtex-series from Xilinx. This paper discusses the exact power consumption trade-offs between the measured runtime consumption of a mapped application and the measured reconfiguration-time consumption of different dynamically (partially and completely) reconfigured applications. Moreover, the possibilities and limitations of today's available power estimation tools are discussed and compared to the exact measurements.

Rambo II: rapidly reconfigurable atomic memory for dynamic networks

Abstract: This paper presents a new algorithm implementing reconfigurable atomic read/write memory for highly dynamic environments. The original RAMBO algorithm, recently developed by Lynch and Shvartsman [15, 16], guarantees atomicity for arbitrary patterns of asynchrony, message loss, and node crashes. RAMBO II implements a different approach to establishing new configurations: instead of operating sequentially, the new algorithm reconfigures aggressively, transferring information from old configurations to new configurations in parallel. This improvement substantially reduces the time to establish a new configuration and to remove obsolete configurations. This, in turn, substantially increases fault tolerance and reduces the latency of read/write operations when the network is unstable or reconfiguration is bursty. This paper presents RAMBO II ,a correctness proof, and a conditional analysis of its performance. Preliminary empirical studies illustrate the advantages of the new algorithm.

SITAR: a scalable intrusion-tolerant architecture for distributed services

Abstract: This paper presents a intrusion tolerant architecture for distributed services, especially COTS servers. An intrusion tolerant system assumes that attacks will happen, and some will be successful. However, a wide range of mission critical applications need to provide continuous service despite active attacks or partial compromise. The proposed architecture emphasizes on continuity of operation. It strives to mitigate the effects of both known and unknown attack. We make use techniques of fault tolerant computing, specifically redundancy, diversity, acceptance test, textitvoting—, as well as adaptive reconfiguration. Our architecture consists of five functional components that work together to extend the fault tolerance capability of COTS servers. In addition, the architecture provides mechanisms to audit the COTS servers and internal components for signs of compromise. The auditing as well as adaptive reconfiguration components evaluate the environment threats, identify potential sources of compromise and adaptively generate new configurations for the system.

Dynamic reconfiguration: Basic building blocks for autonomic computing on IBM pSeries servers

Abstract: A logical partition in an IBM pSeriesTM symmetric multiprocessor (SMP) system is a subset of the hardware of the SMP that can host an operating system (OS) instance. Dynamic reconfiguration (DR) on these logically partitioned servers enables the movement of hardware resources (such as processors, memory, and I/O slots) from one logical partition to another without requiring reboots. This capability also enables an autonomic agent to monitor usage of the partitions and automatically move hardware resources to a needy OS instance nondisruptively. Today, as SMPs and nonuniform memory access (NUMA) systems become larger and larger, the ability to run several instances of an operating system(s) on a given hardware system, so that each OS instance plus its subsystems scale or perform well, has the advantage of an optimal aggregate performance, which can translate into cost savings for customers. Though static partitioning provides a solution to this overall performance optimization problem, DR enables an improved solution by providing the capability to dynamically move hardware resources to a needy OS instance in a timely fashion to match workload demands. Hence, DR capabilities serve as key building blocks for workload managers to provide self-optimizing and self-configuring features. Besides dynamic resource balancing, DR also enables Dynamic Capacity Upgrade on Demand, and self-healing features such as Dynamic CPU Sparing, a winning solution for users in this age of rapid growth in Web servers on the Internet.

Deployment and dynamic reconfiguration planning for distributed software systems

Abstract: Initial deployment and subsequent dynamic reconfiguration of a software system is difficult because of the interplay of many interdependent factors, including cost, time, application state, and system resources. As the size and complexity of software systems increases, procedures (manual or automated) that assume a static software architecture and environment are becoming untenable. We have developed a novel technique for carrying out the deployment and reconfiguration planning processes that leverages recent advances in the field of temporal planning. We describe a tool called Planit, which manages the deployment and reconfiguration of a software system utilizing a temporal planner. Given a model of the structure of a software system, the network upon which the system should be hosted, and a goal configuration, Planit will use the temporal planner to devise possible deployments of the system. Given information about changes in the state of the system, network and a revised goal, Planit will use the temporal planner to devise possible reconfigurations of the system. We present the results of a case study in which Planit is applied to a system consisting of various components that communicate across an application-level overlay network.

Networks on chip as hardware components of an OS for reconfigurable systems

Abstract: In complex reconfigurable SoCs, the dynamism of applications requires an efficient management of the platform. To allow run-time allocation of resources, operating systems and reconfigurable SoC platforms should be developed together. The operating system requires hardware support from the platform to abstract the reconfigurable resources and to provide an efficient communication layer. This paper presents our work on interconnection networks which are used as hardware support for the operating system. We show how multiple networks interface to the reconfigurable resources, allow dynamic task relocation and extend OS-control to the platform. An FPGA implementation of these networks supports the concepts we describe.

Using run-time reconfiguration for fault injection applications

Abstract: The probability of faults occurring in the field increases with the evolution of the CMOS technologies. It becomes, therefore, increasingly important to analyze the potential consequences of such faults on the applications. Fault injection techniques have been used for years to validate the dependability level of circuits and systems, and approaches have been proposed to analyze very early in the design process the functional consequences of faults. These approaches are based on the high-level description of the circuit or system and classically use simulation. Recently, hardware emulation on FPGA-based systems has been proposed to accelerate the experiments; in that case, an important characteristic is the time to reconfigure the hardware, including re-synthesis, place and route, and bitstream downloading. In this paper, an alternative approach is proposed, based on hardware emulation and run-time reconfiguration. Fault injection is carried out by direct modifications in the bitstream, so that re-synthesizing the description can be avoided. Moreover, with some FPGA families (e.g., Virtex or AT6000), it is possible to reconfigure the hardware partially at run-time. Important time-savings can be achieved when taking advantage of these features, since the injection of a fault necessitates the reconfiguration of only a few resources of the device. The injection process is detailed for several types of faults and experimental results are discussed.

On scheduling optical packet switches with reconfiguration delay

Abstract: Using optical technology for the design of packet switches/routers offers several advantages such as scalability, high bandwidth, power consumption, and cost. However, reconfiguring the optical fabric of these switches requires significant time under current technology (microelectromechanical system mirrors, tunable elements, bubble switches, etc.). As a result, conventional slot-by-slot scheduling may severely cripple the performance of these optical switches due to the frequent fabric reconfiguration that may entail. A more appropriate way is to use a time slot assignment (TSA) scheduling approach to slow down the scheduling rate. The switch gathers the incoming packets periodically and schedules them in batches, holding each fabric configuration for a period of time. The goal is to minimize the total transmission time, which includes the actual traffic-sending process and the reconfiguration overhead. This optical switch scheduling problem is defined in this paper and proved to be NP-complete. In particular, earlier TSA algorithms normally assume the reconfiguration delay to be either zero or infinity for simplicity. To this end, we propose a practical algorithm, ADJUST, that breaks this limitation and self-adjusts with different reconfiguration delay values. The algorithm runs at O(/spl lambda/N/sup 2/logN) time complexity and guarantees 100% throughput and bounded worst-case delay. In addition, it outperforms existing TSA algorithms across a large spectrum of reconfiguration values.