Control reconfiguration

About: Control reconfiguration is a research topic. Over the lifetime, 22423 publications have been published within this topic receiving 334217 citations.

Integrating adaptive on-chip storage structures for reduced dynamic power

Abstract: Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies have analyzed individual structures and their control. A common theme to these studies is exploration of the configuration space and use of system IPC as feedback to guide reconfiguration. However when multiple structures adapt in concert, the number of possible configurations increases dramatically, and assigning causal effects to IPC change becomes problematic. To overcome this issue, we introduce designs that are reconfigured solely on local behavior. We introduce a novel cache design that permits direct calculation of efficient configurations. For buffer and queue structures, limited histogramming permits precise resizing control. When applying these techniques we show energy savings of up to 70% on the individual structures, and savings averaging 30% overall for the portion of energy attributed to these structures with an average of 2.1% performance degradation.

Topology design and bandwidth allocation in ATM nets

Abstract: The design of a P/S network embedded into a backbone facility network is discussed. The problem is formulated as a network optimization problem where a congestion measure based on the average packet delay is minimized, subject to capacity constraints posed by the underlying facility trunks. The variables in this problem are the routing on the express pipes (i.e. the channels that interconnect the P/S modes) and the allocation of bandwidth to such pipes. An efficient algorithm is presented for the solution of the above problem and it is applied to some representative examples. It is shown that for some test cases the congestion measure is substantially reduced with respect to the values obtained when the embedded topology is kept identical to the backbone topology. Dynamic reconfiguration schemes where the embedded topology is periodically adjusted to track the fluctuations in traffic requirements are discussed. >

Selection of partners in virtual enterprise paradigm

Abstract: Agility is the competitive advantage in the global manufacturing environment. It is believed that the agility can be realized by dynamically reconfigurable virtual enterprise. However, the configuration of virtual enterprises is a challenge to us. In selecting the partners for the reconfiguration of virtual enterprise, many factors should be taken into consideration. However, the manufacturing cost and time to market are the most important factors. In this paper, in considering the completion time as a constraint we model the partner selection problem by an integer programming formulation to minimize the manufacturing cost. The formulation is then transformed into a graph-theoretical formulation and a 2-phase algorithm is developed to solve the problem. In the first phase, a polynomial bounded algorithm is proposed to find the earliest completion time, so we obtained a feasible solution. In phase 2, we improve the solution by exchanging the candidate partners in keeping the solution in the feasible region. Although we may not find the optimal solution for the problem by the improvement algorithm, the objective is reduced iteration by iteration. Thus, the algorithm is efficient and can be applicable to practical problems. An illustrative example is presented to show the application of the proposed algorithm.

Reconfigurable signal processor

Abstract: An interconnection scheme among the processing elements ("PEs") of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different processing topologies including binary trees and linear systolic arrays. By using a novel variant on a tree expansion scheme, the invention also allows for arbitrary up-sizing of the PE count to build virtually any size of tree network, with each size exhibiting same high degree of fault tolerance and reconfigurability. The invention may be practiced with 4-port PEs arrayed in a module comprising a 4×4 board-mounted PE lattice. Each PE has four physical ports, which connect to the similar ports of its lattice neighbors. Each PE has an internal capability to be configured to route signals to or from any of its neighbors. Thus, for tree topologies, any of the four neighbors of a given PE may be selected as the parent of the given PE; and any or all of the remaining three neighboring PEs may be selected as the child(ren) PEs. The PE ports are configured under the control of a remote host, which establishes an initial desired PE topology. The operability of the PEs is tested, and information on faulty PEs or communications paths is used to enable or disable nodes as necessary by revising the PE port configurations. The nodes thus are reorganized and can run or continue running, on a degraded basis.