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Copper plating

About: Copper plating is a research topic. Over the lifetime, 11163 publications have been published within this topic receiving 99679 citations.


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Journal ArticleDOI
TL;DR: The challenges of filling trenches and vias with Cu without creating a void or seam are reviewed, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage is found.
Abstract: Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.

1,098 citations

01 Jan 1999
TL;DR: Damascene copper electroplating for on-chip interconnections, a process that was conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition as discussed by the authors.
Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

1,006 citations

Patent
Bin Zhao1, P. K. Vasudev1, Valery M. Dubin1, Yosef Shacham-Diamand1, Chiu H. Ting1 
16 Jan 1996
TL;DR: In this article, a via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD, and an electroless copper deposition technique is used to auto-catalytically deposit copper in the via.
Abstract: A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via. The plug is then annealed.

502 citations

Journal ArticleDOI
TL;DR: It is shown that cuprous intermediates near the copper surface affect the overpotential and the kinetics of plating, and the additives regulate the presence of cuprous species on the surface; levelers and suppressors inhibit Cu+ formation, whereas accelerating additives enhance Cu- formation.
Abstract: Copper plating baths used for forming integrated circuit interconnects typically contain three or four component additive mixtures which facilitate the superfilling of via holes and trench lines during damascene plating. Extensive study over the last two decades has provided researchers with an understanding of the underlying mechanisms. The role of cuprous intermediates in the copper deposition reaction has long been acknowledged, but it is not yet fully understood. In this paper we describe the results of an electrochemical study of the interaction of the organic additives used with copper and copper ions in solution. It is shown that cuprous intermediates near the copper surface affect the overpotential and the kinetics of plating. The additives regulate the presence of cuprous species on the surface; levelers and suppressors inhibit Cu+ formation, whereas accelerating additives enhance Cu+ formation. Acceleration by the bis(sodiumsulfopropyl) disulfide (SPS) additive results from accumulation of cuprous complexes near the surface. Adsorbed cuprous thiolate [Cu(I)(S(CH2)3 SO3H)ad] is formed through interaction of Cu+ ions and SPS rather than Cu2+ and mercaptopropane sulfonic acid (MPS).

429 citations

Journal ArticleDOI
05 Oct 2001-Science
TL;DR: Device-quality copper and nickel films were deposited onto planar and etched silicon substrates by the reduction of soluble organometallic compounds with hydrogen in a supercritical carbon dioxide solution, providing a single-step means for achieving high-aspect-ratio feature fill necessary for copper interconnect structures in future generations of integrated circuits.
Abstract: Device-quality copper and nickel films were deposited onto planar and etched silicon substrates by the reduction of soluble organometallic compounds with hydrogen in a supercritical carbon dioxide solution. Exceptional step coverage on complex surfaces and complete filling of high-aspect-ratio features of less than 100 nanometers width were achieved. Nickel was deposited at 60°C by the reduction of bis(cyclopentadienyl)nickel and copper was deposited from either copper(I) or copper(II) compounds onto the native oxide of silicon or metal nitrides with seed layers at temperatures up to 200°C and directly on each surface at temperatures above 250°C. The latter approach provides a single-step means for achieving high-aspect-ratio feature fill necessary for copper interconnect structures in future generations of integrated circuits.

404 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202327
202271
202184
2020255
2019327
2018363