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Crossbar switch

About: Crossbar switch is a(n) research topic. Over the lifetime, 12588 publication(s) have been published within this topic receiving 175968 citation(s). The topic is also known as: crossbar.

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Papers
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Journal ArticleDOI: 10.1038/NMAT3070
Myoung-Jae Lee1, Chang Bum Lee1, Dongsoo Lee1, Seung Ryul Lee1  +9 moreInstitutions (2)
01 Aug 2011-Nature Materials
Abstract: Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

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Topics: Universal memory (56%), Semiconductor memory (56%), Non-volatile memory (56%) ...read more

1,693 Citations


Open accessJournal ArticleDOI: 10.1038/NATURE14441
07 May 2015-Nature
Abstract: Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

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Topics: Neuromorphic engineering (69%), Memristor (53%), Integrated circuit (51%) ...read more

1,688 Citations


Open accessJournal ArticleDOI: 10.1038/NMAT2028
Wei Lu1, Charles M. Lieber2Institutions (2)
01 Nov 2007-Nature Materials
Abstract: Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

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Topics: Nanoelectronics (56%), Crossbar switch (52%), Electronics (50%)

1,469 Citations


Open accessJournal ArticleDOI: 10.1109/90.769767
Nick McKeown1Institutions (1)
Abstract: An increasing number of high performance internetworking protocol routers, LAN and asynchronous transfer mode (ATM) switches use a switched backplane based on a crossbar switch. Most often, these systems use input queues to hold packets waiting to traverse the switching fabric. It is well known that if simple first in first out (FIFO) input queues are used to hold packets then, even under benign conditions, head-of-line (HOL) blocking limits the achievable bandwidth to approximately 58.6% of the maximum. HOL blocking can be overcome by the use of virtual output queueing, which is described in this paper. A scheduling algorithm is used to configure the crossbar switch, deciding the order in which packets will be served. Previous results have shown that with a suitable scheduling algorithm, 100% throughput can be achieved. In this paper, we present a scheduling algorithm called iSLIP. An iterative, round-robin algorithm, iSLIP can achieve 100% throughput for uniform traffic, yet is simple to implement in hardware. Iterative and noniterative versions of the algorithms are presented, along with modified versions for prioritized traffic. Simulation results are presented to indicate the performance of iSLIP under benign and bursty traffic conditions. Prototype and commercial implementations of iSLIP exist in systems with aggregate bandwidths ranging from 50 to 500 Gb/s. When the traffic is nonuniform, iSLIP quickly adapts to a fair scheduling policy that is guaranteed never to starve an input queue. Finally, we describe the implementation complexity of iSLIP. Based on a two-dimensional (2-D) array of priority encoders, single-chip schedulers have been built supporting up to 32 ports, and making approximately 100 million scheduling decisions per second.

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  • Fig. 9. Illustration of 100% throughput foriSLIP caused by desynchronization of output arbiters. Note that pointers[gi] become desynchronized at the end of Cell 1 and stay desynchronized, leading to an alternating cycle of 2 cell times and a maximum throughput of 100%.
    Fig. 9. Illustration of 100% throughput foriSLIP caused by desynchronization of output arbiters. Note that pointers[gi] become desynchronized at the end of Cell 1 and stay desynchronized, leading to an alternating cycle of 2 cell times and a maximum throughput of 100%.
  • Fig. 16. Example of the number of iterations required to converge for a heavily loadedN N switch. All input queues remain nonempty for the duration of the example. In the first cell time, the arbiters are all synchronized. During each cell time, one more arbiter is desynchronized from the others. After N cell times, all arbiters are desynchronized and a maximum sized match is found in a single iteration.
    Fig. 16. Example of the number of iterations required to converge for a heavily loadedN N switch. All input queues remain nonempty for the duration of the example. In the first cell time, the arbiters are all synchronized. During each cell time, one more arbiter is desynchronized from the others. After N cell times, all arbiters are desynchronized and a maximum sized match is found in a single iteration.
  • Fig. 17. Performance ofiSLIP for 1, 2, and 4 iterations compared with FIFO and output queueing for i.i.d. Bernoulli arrivals with destinations uniformly distributed over all outputs. Results obtained using simulation for a 16 16 switch. The graph shows the average delay per cell, measured in cell times, between arriving at the input buffers and departing from the switch.
    Fig. 17. Performance ofiSLIP for 1, 2, and 4 iterations compared with FIFO and output queueing for i.i.d. Bernoulli arrivals with destinations uniformly distributed over all outputs. Results obtained using simulation for a 16 16 switch. The graph shows the average delay per cell, measured in cell times, between arriving at the input buffers and departing from the switch.
  • Fig. 3. Example of unfairness for PIM under heavy oversubscribed load with more than one iterations. Because of the random and independent selection by the arbiters, output 1 will grant to each input with probability 1/2, yet input 1 will only accept output 1 a quarter of the time. This leads to different rates at each output.
    Fig. 3. Example of unfairness for PIM under heavy oversubscribed load with more than one iterations. Because of the random and independent selection by the arbiters, output 1 will grant to each input with probability 1/2, yet input 1 will only accept output 1 a quarter of the time. This leads to different rates at each output.
  • Fig. 14. Comparison of analytical approximation and simulation results for the average number of synchronized output schedulers. Simulation results are for a 16 16 switch with i.i.d. Bernoulli arrivals and an on–off process modulated by a two-state Markov chain with an average burst length of 64 cells. The analytical approximation is shown in (3).
    Fig. 14. Comparison of analytical approximation and simulation results for the average number of synchronized output schedulers. Simulation results are for a 16 16 switch with i.i.d. Bernoulli arrivals and an on–off process modulated by a two-state Markov chain with an average burst length of 64 cells. The analytical approximation is shown in (3).
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Topics: Load-balanced switch (57%), Crossbar switch (54%), Scheduling (computing) (54%) ...read more

1,243 Citations


Journal ArticleDOI: 10.1038/NMAT2748
Eike Linn1, R. Rosezin2, Carsten Kügeler2, Rainer Waser1  +1 moreInstitutions (2)
01 May 2010-Nature Materials
Abstract: On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

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Topics: Crossbar switch (59%), Energy consumption (53%), Logic gate (51%)

1,099 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
2021155
2020203
2019209
2018205
2017243

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Topic's top 5 most impactful authors

Siyuan Yu

30 papers, 248 citations

Makoto Miyamura

18 papers, 152 citations

Chris Yakopcic

16 papers, 208 citations

R. Stanley Williams

15 papers, 2.8K citations

Manolis Katevenis

14 papers, 310 citations

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