About: Decoupling capacitor is a(n) research topic. Over the lifetime, 12282 publication(s) have been published within this topic receiving 141890 citation(s). The topic is also known as: bypass capacitor.
Papers published on a yearly basis
Abstract: We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.
Abstract: Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.
••23 Feb 1997
Abstract: A clocked switched-capacitor circuit can exchange charge between adjacent batteries in a series string. This exchange drives all batteries to identical voltages, without regard to component values, battery technology, or state of charge. This equalization process can proceed while the batteries are in use or under charge, or separately. Transformer-based and transformerless implementations are given, and results of experimental tests are provided. The process is much faster and less stressful than the conventional approach, and is simpler than some active approaches.
Abstract: The reliability of the microinverter is a very important feature that will determine the reliability of the ac-module photovoltaic (PV) system. Recently, many topologies and techniques have been proposed to improve its reliability. This paper presents a thorough study for different power decoupling techniques in single-phase microinverters for grid-tie PV applications. These power decoupling techniques are categorized into three groups in terms of the decoupling capacitor locations: 1) PV-side decoupling; 2) dc-link decoupling; and 3) ac-side decoupling. Various techniques and topologies are presented, compared, and scrutinized in scope of the size of decoupling capacitor, efficiency, and control complexity. Also, a systematic performance comparison is presented for potential power decoupling topologies and techniques.
13 Jun 1997
TL;DR: A new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors based on an integrated package-level and chip-level power bus model, and a simulated switching circuit model for each functional block offers the most complete and accurate analysis of Vdd distribution.
Abstract: This paper describes a new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors.Based on an integrated package-level andchip-level power bus model, and a simulated switching circuitmodel for each functional block, this methodology offersthe most complete and accurate analysis of Vdd distributionfor the entire chip. The analysis results not only providedesigners with the inductive ΔI noise and the resistive IRdrop data at the same time, but also allow designers to easilyidentify the hot spots on the chip and ΔV across the chip.Global and local optimization such as buffer sizing, powerbus sizing, and on-chip decoupling capacitor placement canthen be conducted to maximize the circuit performance andminimize the noise.
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