Showing papers on "Decoupling capacitor published in 1985"

Integrated circuit sensor

Abstract: A polysilicon microstructure is formed on a silicon substrate. Beneath the microstructure, are diffused regions in the substrate. The microstructure is capacitively coupled to these diffused regions so that one such capacitor acts as an excitation capacitor and the other capacitor acts as a sense capacitor. By applying an AC voltage to the excitation capacitor, the electrostatic force between the substrate and the microstructure changes causing a mechanical vibration in the microstructure. A DC voltage is applied to the sense capacitor. The mechanical vibration, which changes its capacitance, will develop a current through the sense capacitor. A phenomenon may then be sensed by the vibrating microstructure. A polymer film disposed on the microstructure can sorb a gas of interest. As the mass of the polymer film and vibrating microstructure increases, its frequency or phase changes. The current through the sense capacitor will exhibit a commensurate frequency or phase shift. Detection of such frequency or phase shift in the sense capacitor current will transduce the detection of the vapor of interest.

High voltage apparatus

Abstract: The invention provides a high voltage capacitor suitable for measuring the voltage of an overhead power line. The capacitor dielectric (16B) is mounted directly on to the power line conductor (2), which serves as one electrode of the capacitor. The other electrode (18) of the capacitor is mounted on to the outer surface of the dielectric (16B), and is protected at each side by a guard ring (20). Stress control (22, 24) is provided between the outer capacitor electrode (18) and the guard rings (20) and also at the outer edges of the guard rings (20). The capacitor may be enclosed in an earthed housing (30). which can contain one or more current transformers (34, 36, 38). The apparatus can be used for fault detection and location, and may be used in combination with a power cable or a switch.

Self-calibration method for capacitors in a monolithic integrated circuit

Abstract: A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted. In another aspect of the invention, capacitance-adjustment steps are sequentially interleaved with analog-to-digital conversions in an analog-to-digital converter.

Wafer-scale-integrated assembly.

Abstract: The silicon wafer (54) of a wafer-scale-integrated assembly is doped to render it highly conductive. Additionally, a conductive layer (56) is formed on the bottom of the wafer. The bottom-side layer forms an easily accessible ground plane of the assembly. Moreover, this layer and the conductive silicon constitute one plate of an advantageous wafer-size decoupling capacitor. A nearly continuous power layer (58) and a relatively thick layer (60) of silicon dioxide on the top side of the assembly form the other elements of the decoupling capacitor. Additionally, the nearly continuous power layer constitutes an effective a-c ground plane for overlying signal lines.

Discharge lamp starting circuit particularly for compact fluorescent lamps

Abstract: To provide for reliable ignition of low-pressure discharge lamps, particularly compact fluorescent lamps, operated at high frequency, for example in the order of about 45 kHz, an ignition circuit is connected in parallel to the lamp and serially with the electrodes (16, 17) thereof, which comprises a limiting capacitor (19) and the parallel circuit of a positive temperature coefficient (PTC) resistor (20) and a starting capacitor (18). The two capacitors (18, 19), together with an inductance (13, 14) in the operating circuit of the lamp, and a further capacity formed by a blocking capacitor (15), after preheating of the lamp electrodes by current flowing through the initially cold PTC resistor, will cause voltage rise across the resonance capacitors (18, 19) which will cause ignition of the lamp. The ratio of the limiting capacitor to the starting capacitor is in the order of 1:1 to 5:1, preferably about 2:1, resulting in gentle ignition in minimum time, for example about 1/2 second after energization of the lamp.

Electrical excitation circuit for gas lasers

Abstract: An electrical excitation circuit (10) for a gas laser. The electrical excitation circuit includes a charging circuit (16), connected in series with a pulse forming network (18) between a power source (12) and the laser load (14). The charging circuit (10) includes a capacitor charged by the power source (12) and a thyratron (S1) for transferring voltage to the pulse forming network (18). Alternatively, the charging circuit (10) includes a capacitor charged upon the firing of a silicon controlled rectifier (SCR1) through a saturable step-up transformer (XFMR1) which saturates for transferring voltage to the pulse forming network (18). The pulse forming network (18) includes a saturable inductor switch (S2) positioned with respect to a capacitor so that, when the voltage on the capacitor reaches a predetermined level, saturation on the saturable inductor switch (S2) releases electrical energy stored in the capacitor to the laser load (14). The saturable inductor switch (S2) is biaised by means of an electrical bias current which can be adjusted so that the saturable inductor switch (S2) saturates after the capacitor is fully charged, thereby controlling the time of application of the high voltage pulse to the laser load (14). The pulse forming network (18) preferably includes an additional capacitor and a magnetic diode charging inductor (L3) which is also biased by means of an electrical bias current. The capacitor is charged through the magnetic diode charging inductor (L3) and discharges in series with the other capacitor when the saturable inductor switch (S2) saturates, thereby doubling the voltage across the laser load (14) at the time of discharge. The magnetic diode charging inductor (L3) also minimizes prepulse across the laser load (14) during charging of the additional capacitor. Neither the saturable inductor switch (S2) nor the magnetic diode charging inductor (L3) are in the discharge loop (LD) with the laser load (14) thereby minimizing the inductance of the discharge loop (LD).

Soft-start capacitor discharge circuit

Abstract: In a switched mode power supply during start-up, an increasing charge on a soft-start capacitor controls a pulse width modulator for increasing the length of drive pulses provided to a pair of switching transistors until a reference voltage level is reached, after which stable power supply operation ensues. Detection circuitry senses a low power supply output voltage such as arising from input line interruptions and rapidly discharges the soft-start capacitor and prevents the recurrence of the soft-start mode of operation before the soft-start capacitor is fully discharged to prevent overloading of power supply output semiconductor devices upon the resumption of normal input voltage to the power supply.

Capacitance transducing method and apparatus

Abstract: A signal generating circuit useful in determining the value of a capacitor includes a charging source having a resistive element and a plurality of switches, each switch being positionable between a first, open position and a second, closed position in response to logic signals. The switches are thereby controllable for sequentially connecting a first reference capacitor of known value and a second capacitor to the resistive element for charging said capacitors to a potential. An oscillating comparator network establishes a trigger reference voltage and generates a clocking pulse when the sequentially detected charge potential of the capacitors is equal to the trigger reference voltage. A logic network is connected to the comparator network for generating the logic signals in response to the clocking pulse and the logic network includes a network for resetting the signal generating circuit. Also included is means for determining a first time required to charge the first capacitor from an initially-depleted state to the trigger reference voltage and for determining a second time required to charge the second capacitor from an initially-depleted state to the trigger reference voltage. A method for determining the value of a capacitance is also disclosed.

DC offset correction circuit utilizing switched capacitor differential integrator

Abstract: An integrated circuit employing a differential integrator and switched capacitor network to provide auto-zeroing. The differential integrator utilizes a feedback circuit between its inputs and outputs. A switched capacitor network coupled to the inputs of the amplifier provides voltage division of differential reference signals which determine the amount of DC offset. The amplifier then integrates the reference signals to a predetermined time constant, wherein the average voltage of the output of the integrator is used to provide auto-correction of the DC offset. A second switched capacitor voltage divider network and a second differential integrator cascaded to the first circuit provides a second time constant for fine-tuning the auto-correction signal.

Series capacitor equipment

Abstract: A series capacitor bank for connection into an electric power supply network is provided with overvoltage protective equipment having two branches connected in parallel with the capacitor bank. The first branch comprises a first zinc oxide varistor in series with a linear resistor and the second branch comprises a varistor with a higher "knee" voltage than the first zinc oxide varistor. The resistance of the linear resistor is preferably of the same order of magnitude as the absolute value of the impedance of the capacitor bank at the operating frequency of the power supply network. The "knee" voltage of the second varistor is at least 1.15 times (and preferably not more than 2.0 times) the "knee" voltage of the first varistor.

Efficient power amplifier for high capacitive devices

Abstract: An efficient power amplifier for high-capacitive device C2 in load string 10. The load string 10 includes a reference capacitor C3, a resistor R1, and an inductor L1. A large capacitor C1 is connected to load string 10 through high voltage power bridge 28. A current sensing feedback 30 is utilized to produce a triangular waveform of current in load string 10 for causing charge to be alternatively removed from capacitor C1 and delivered to device C2 through inductor L1 and then returned to capacitor C1 with any losses replenished by the dc power source. A voltage sensing feedback 14 is used to modulate the triangular current waveform. The power amplifier behaves as a stable linear dc coupled operational amplifier delivering a large reactive current with only slight losses.

Dual rank sample and hold circuit and method

Abstract: A dual rank sample and hold circuit and method, particularly applicable to deglitching the output of a digital-to-analog converter. One signal path is provided for coupling an input signal to the output of the sample and hold circuit to track the input signal during sampling. A second signal path is provided for coupling the input signal to a storage capacitor for charging or discharging the capacitor to the level of the input signal. In one embodiment the output is coupled simultaneously via the first signal path to theJnput signal and through a resistor to the storage capacitor/during a sampling phase, the capacitor being coupled to the input signal, and thereafter only to the capacitor during a hold phase, the capacitor being decoupled from the input signal. In another embodiment the output is coupled alternatively through the first signal path to the input signal during a sampling phase, the capacitor being coupled to the input signal, and thereafter to the capacitor during a hold phase, the capacitor being decoupled from the input signal. In application to a digital-to-analog converter sampling begins after the analog output signal settles and ends prior to the next conversion event, and hold lasts past the next conversion event to the next sample.

Capacitive transducer and method

Abstract: An integrated circuit capacitive transducer (10) measures at least one parameter of a medium to which it is exposed. A variable capacitor (12) has a capacitance (C1) which varies as a function of the measured parameter and is charged by source of reference potential (Vr). The charge on the variable capacitor (12) is then transferred to a second capacitor (14) having a fixed reference capacitance (Cr). The voltage (V1) developed across the second capacitor (14) by the charge transferred thereto is then a function of the capacitance (Vr) of the first capacitor (12). Therefore, the voltage (V1) is also a function of the parameter being measured. The capacitive transducer may also include a further variable capacitor (32, 34) for measuring the difference of parameters between two mediums.

Analog signal conditioning and digitizing integrated circuit

Abstract: An analog signal conditioning and digitizing integrated circuit is provided having a multiplying digital to analog converter means (MDAC) including a gain capacitor array and an offset capacitor array, an operational amplifier, a feedback circuit including a feedback capacitor and a feedback clamping transistor, the operational amplifier and feedback circuit connected to the gain and offset capacitor arrays for setting the gain and the amount of offset correction of the MDAC, a correlated double sample circuit including a series capacitor connected to the operational amplifier and a series clamping transistor connected to the junction of the series capacitor and a buffer amplifier for sampling the noise to be substracted and/or nulled across the series capacitor, and an analog to digital converter operatively connected to the MDAC for digitizing the output of the MDAC. In other embodiments the integrated circuit has separate bond pads for the analog signal inputs and outputs of the MDACs and DACs or for implementing feedback/feedforward discrete time transfer functions.

Structure of power supply wirings in semiconductor integrated circuit

Abstract: A semiconductor device comprises a first circuit section positioned in a center portion of the substrate, a second circuit section provided in the peripheral portion of the substrate, and first to third power supply main wiring layers on the substrate. The first wiring layer supplies a first voltage such as ground potential to the second circuit section. The second wiring layer supplies a second voltage such as Vcc potential to the second circuit section. The third wiring layer supplies the first voltage to the first circuit section. The device further comprises a MOS type capacitor having upper and lower electrodes. The upper electrode of the capacitor is connected to the second wiring layer, and the lower electrode of the capacitor is connected at its end parts to the first and third wiring layers such that both wiring layers are electrically connected each other. Such a device can decrease the surge current induced in the wiring layers by the capacitor. Further, signal lines can be continuously formed with low electrical resistance on an insulating layer above the capacitor. Therefore, the access time of the device can be reduced.

Ignition circuit for high pressure arc discharge lamps

Abstract: Apparatus for igniting and operating a high pressure arc discharge lamp includes a pulse generating circuit for generating high voltage pulses for starting the lamp. The pulse generating circuit is comprised of a step-up transformer, a start capacitor, a voltage sensitive bidirectional switch (e.g., a sidac) and an impedance which forms a charge circuit for the capacitor. The capacitor discharges via the switch and a part of the transformer to generate a high voltage pulse which is coupled to the lamp electrodes. An auxiliary capacitor and a serially connected inductor are coupled in parallel with the pulse generating circuit so as to clamp the open circuit voltage at a high level upon generation of the ignition pulse thereby to maintain a level of lamp current sufficient to sustain the discharge arc. This makes the lamp ignition more reliable and extends the lamp life.

Flat decoupling capacitor and method of manufacture thereof

Abstract: A flat decoupling capacitor having incorporated therein a multilayer chip capacitor which provides high capacitance values, local charge storage and noise decoupling for integrated circuits is presented. The decoupling capacitor essentially comprises at least two conductors electrically connected to a multilayer ceramic capacitor chip, all of which are encapsulated by an insulating material. Several embodiments are described having variations in chip dimensions, number of multilayer capacitors, number of conductors and particular structural configuration. A simplified embodiment and method of manufacture thereof is also presented.

Current metering apparatus for optimally inducing field emission of electrons in tunneling devices and the like

Abstract: A current metering circuit is configured as a single stage charge pump for limiting the current level applied to the tunneling regions of an integrated circuit, nonvolatile, floating gate memory cell. The current metering circuit includes a storage capacitor which has one plate pumped by a periodic signal. The other plate of the capacitor is charged from a voltage that is boot-strapped from the voltage that presently exists across the active tunneling region. More particularly, a high voltage is applied to the drain of a transistor whose gate is connected to the tunneling region. The source of this transistor is coupled to a plate of the storage capacitor. This source develops a voltage equal to the present voltage across the load less the turnon threshold of the transistor. When the periodic signal goes low, the storage capacitor is charged from the voltage appearing at the source of this transistor. When the periodic signal goes high, this transistor is biased to turn off and the capacitor discharges through a diode to develop the metered output current. The current amplitude is equal to the product of the capacitance of the storage capacitor, the change in voltage across the capacitor in each cycle and the frequency of the periodic signal.

Audio amplifier switch-on control circuit

Abstract: A capacitor which is progressively chargeable in response to a switching on of the equipment, however brought about, is associated with an oscillating circuit with intervention threshold. As the load voltage of said capacitor increases the oscillating circuit shifts from a first to a second operating state, generating a switch-on current for the audio amplifier. The latter can be placed in stand-by condition by discharging to earth said capacitor by means of a suitable switch.

Vertical deflection circuit for electron beams in picture tubes

Abstract: A voltage of a sawtooth generator is present at a capacitor. This voltage is compared to a reference voltage. In case of a deviation, a controllable current source is connected in parallel to a constant current source charging the capacitor. This allows the position of the picture to be maintained fixed by keeping the center of the picture at a preset level. A counter circuit counts lines of a screen picture and produces a control signal. An electronic switch is connected to the counter circuit and to the capacitor for periodically discharging the capacitor after a vertical deflection period triggered by the control signal of the counter circuit. A first comparator circuit is connected to the counter circuit and activated by a signal from the counter circuit and further connected to the capacitor for comparing the actual voltage applied at the capacitor to a reference voltage. A vertical deflection output stage has an input connected to the capacitor. The constant current source is connected to the capacitor for charging the capacitor with a charging current to provide a control signal for the vertical deflection output stage. The controllable current source is connected in parallel relative to the constant current source for controlling the charging current of the capacitor such that the voltage of the capacitor corresponding to the center of the picture screen is maintained at a constant value.

Semiconductor integrated circuit device formed with a CMOS circuit and a boatstrap capacitor

Abstract: A circuit is formed with a combination of a CMOS circuit and a bootstrap capacitor connected to an output terminal of the CMOS circuit in order to reduce the power consumption and to obtain, at the output terminal, a high output voltage exceeding a power supply voltage. In order to prevent the discharge of the bootstrap capacitor, a switching element for preventing a reverse biasing state of the MOSFET on the power supply side of the CMOS circuit is connected in series with the MOSFET.

Latching relay drive circuit for use in telephone sets

Abstract: In a circuit for driving a latching relay for use in a telephone set, a capacitor is charged from a battery, and when the capacitor is charged to a predetermined value, the capacitor is disconnected from the battery. Thereafter the latching relay is driven by the discharge current of the capacitor. With this circuit, it is possible to prevent unnecessary consumption of the battery.

ECL terminator comprised of a plural resistor network

Abstract: A circuit/packaging arrangement for terminating and decoupling emitter coupled logic comprises a plurality of terminating impedance components (resistors) and decoupling capacitor one end of each of which is connected via a common conductor to one pair of a multi-pin single-in-line package (SIP). The other ends of the terminating impedance and the capacitor are connected to respective terminal pins adjacent to the one pin of the SIP. The decoupling capacitor that is coupled with the terminating resistors is located, both physically and electrically, at the middle of the distribution or terminating resistors contained within the SIP, such that the resistors are distributed effectively/symmetrically on either side of the capacitor. This location of the capacitor effectively in the middle of the terminating network minimizes line inductance of the common (-2v) conductor to which one end of each of the resistors is connected.

A pulse generator

Abstract: The invention relates to a pulse generator of the type comprising a capacitor, means for periodically discharging the capacitor to produce the pulses and means for recharging the capacitor between pulses. There is a problem when, due to fault conditions in the load the capacitor is left with a reverse charge after a pulse. This problem is dealt with by sensing such a residual reverse charge and for discharging the stored energy in such a way that it is used to contribute towards recharging the capacitor for the next pulse.

Low order charge-pump filter

Abstract: The present invention discloses a low order charge-pump filter operable with a single variable current source. The integrating capacitor of the charge-pump is connected in an H-bridge switching configuration with four switches that are operable to control the current source to supply current to a first node of the capacitor or to a second node of the capacitor or to bypass a capacitor, depending on the state of operation of the charge-pump. The charge-pump filter disclosed is particularly useful for providing the low order response for a phase detector in a phase-locked loop.

Electronic device for reduction of the power loss during the generation of a stabilised DC voltage or of a stabilised DC current from an AC voltage source

Abstract: The interconnection of electrically supplied apparatuses to widely varying supply voltages necessitates measures for reduction of the power loss, which is converted into heat, for the apparatuses having a low supply voltage and a relatively high current consumption, with a simultaneous requirement for extreme miniaturisation. For this purpose, when supplied from an AC voltage source, the invention utilises a diode for rectification, the collector-emitter junction of a switching transistor which is connected in series with the diode, and a capacitor which is charged when the switching transistor is in the conducting state. Furthermore, an electronic two-point switch is required which compares the charging voltage of the capacitor with a fixed reference voltage and activates the base of the switching transistor such that a sawtooth-waveform voltage characteristic is produced on the charging capacitor, the fluctuation width of the said characteristic depending on the hysteresis of the two-point switch and on the capacitance of the capacitor. The capacitor is recharged only twice per active rectification phase, namely once on the rising edge, and once on the falling edge, of the pulsating voltage. The former assists in keeping the capacitance of the capacitor small, while the latter minimises the heat conversion.

Decoupling capacitor for surface mounted chip carrier

Abstract: High frequency noise is decoupled from power supplied to a surface mounted integrated circuit (IC) chip carrier package by installation of a surface mounted decoupling capacitor between the IC chip carrier package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of surface mountable leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a surface mounted integrated circuit (IC) chip carrier package and correspond to the power and ground pin configuration of that package.

Ripple and droop reduction circuit

Abstract: A radar transmitter includes a ripple and droop reduction circuit to reduce the ripple and droop of the beam (power) supply. A beam supply filter capacitor is connected to the source of power and an operational amplifier has its balanced input ac connected across the beam supply capacitor. A transistorized amplifier stage inverts the signal from the operational amplifier and amplifies its absolute value up to the same level appearing across the beam supply filter capacitor. A transistorized follower stage is connected to the transistorized amplifier stage for receiving the inverted signal and producing a low impedance output for insertion in series with the beam supply filter capacitor for ripple and droop cancellation. A traveling-wave-tube is connected to the supply power capacitor which receives the ripple and droop free capacitor output and produces substantially consistent pulses for transmission.

Efficient electrical conversion switching tube suitable for inductive loads

Abstract: Disclosed is an electrical driving and recovery system for a high frequency environment. The recovery system can be applied to drive present day direct-current or alternating-current loads for better efficiency. It has a low-voltage source coupled to a vibrator, a transformer and a bridge-type rectifier to provide a high voltage pulsating signal to a first capacitor. Where a high-voltage source is otherwise available, it may be coupled directly to a bridge-type rectifier, causing a pulsating signal to the first capacitor. The first capacitor in turn is coupled to a high voltage anode of an electrical conversion switching element tube. The switching element tube also includes a low voltage anode which is connected to a voltage source by a commutator and a switching element tube. Mounted around the high voltage anode is a charge receiving plate which is coupled to an inductive load to transmit a high voltage discharge from the switching element tube to the load. Also coupled to the load is a second capacitor for storing the back EMF created by the collapsing electrical field of the load when the current to the load is blocked. The second capacitor is coupled to the voltage source. When adapted to present day direct-current or alternating-current devices the load could be a battery or capacitor to enhance the productivity of electrical energy.

Power supply for discharge lamp

Abstract: A power supply circuit comprises a single discharge capacitor having a charging sufficient to trigger discharge in a discharge lamp. The discharge capacitor is associated with means for accumulating energy, with which it is charged. The energy accumulating means receives commercially available alternating current and applies the accumulated energy to the discharge capacitor to charge the latter. The power supply circuit may include an auxiliary capacitor which has a smaller capacitance and higher potential rating than the discharge capacitor. The auxiliary capacitor may have a potential rating sufficient to activate the discharge lamp alone. The discharge capacitor cooperates with the auxiliary capacitor to define discharge period. Preferably, the power supply circuit may include means for blocking or shutting off power supply at a given timing to precisely control the discharge period. Such power supply blocking means is especially advantageous for controlling the quantity of light to be emitted by the discharge lamp. The discharge capacitor and the auxiliary capacitor are controlled so as to perform a two-stage flash which includes a first stage with a brief, relatively strong flash and a second stage with a longer, relatively weak flash. This flash is advantageous for fixing toner images with low- and high-toner-density components. Alternatively, the discharge period may be controlled to within a given period to achieve good fixation of the toner image without causing significant noise or smell.