Showing papers on "Decoupling capacitor published in 1990"

Influence of the terminal capacitor on the performance characteristics of a self excited induction generator

Abstract: The influence of the excitation capacitor on the steady state performance characteristics of an isolated self-excited induction generator feeding a balanced load is examined. It is shown that the terminal capacitor must have its value within a certain range to sustain self-excitation. If the value of the excitation capacitor is outside this range, self-excitation will not be possible. Moreover, if the load impedance is below a certain value, self-excitation will not be achieved irrespective of the value of the excitation capacitor. In the capacitance range where self-excitation is possible, it's value strongly influences the induction generator performance characteristics. The value of capacitance can be selected so that the terminal voltage is constant, regardless of the generator output power. It is further shown that under such condition, the value of capacitance is influenced by the load as well as by the load power factor. The generator performance is however independent of the load power factor and is only affected by the magnitude of the load impedance.

CMOS amplifier with offset adaptation

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

Variable capacitance integrated circuit usable in temperature compensated oscillators

Abstract: A variable capacitance circuit comprising a capacitor array, associated switching elements and transient impedance varying circuits. The capacitor array comprises a plurality of capacitor elements connected to a common node coupled to a crystal oscillator in a crystal oscillator portion and each capacitor element includes a connected switching element that controls activation of selected capacitor elements that are selectively placed in operation as load capacitance with the crystal oscillator to change and adjust its frequency. Further, circuits are provided in a temperature compensation portion to selectively control the activation of the switching elements based upon decoded compensating values provided in memory, such as based upon sensed oscillator temperature conditions. The transient impedance varying circuits comprise multi-level voltage generating circuits for changing the continuity impedance of activated switching elements, among switching elements being switched, to another impedance level or one of a plurality of additional impedance levels. As a result, an intermediate impedance value can be created between the ON and OFF states of the switching elements so that there is no rapid change in the total equivalent capacitance imposed by the capacitor array on the oscillator resulting in smooth capacitance switching which corresponds to smoother frequency adjustment of oscillator output.

Feedforward compensation techniques for high-frequency CMOS amplifiers

Abstract: Two circuit techniques for broadbanding the gain bandwidth product (GBW) of CMOS amplifiers are presented. The conventional feedforward technique using an AC bypass capacitor is reviewed. Compared to the conventional technique, the new techniques offer the advantage of exact cancellation of the low-frequency pole-zero pair. Furthermore, the position of the pole-zero pair occurs at higher frequencies than with the conventional technique. Calculations and computer simulations suggest that using the new techniques. CMOS amplifiers with a unity stable GBW of 160 MHz can be obtained in a standard 3- mu m CMOS technology. >

Adaptable CMOS winner-take all circuit

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation

Abstract: One of the sources of nonlinearity in charge redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. While it is possible to address this problem through capacitor fabrication technology improvements, situations arise where it is more desirable to use circuit techniques. The conventional fully differential charge redistribution converter topology eliminates errors proportional to the capacitor linear voltage coefficient, but its comparator is subjected to the common-mode input signal. When converting unbalanced differential signals, linearity is achieved only with large comparator common-mode rejection. An alternative differential converter topology that isolates the comparator from the input common-mode signal, resulting in a common-mode rejection ratio of -73 dB, is presented. In addition, a circuit that cancels the error caused by the quadratic capacitor voltage coefficient is described. Measurements show that it is capable of increasing the converter linearity by an order of magnitude. >

Internally decoupled integrated circuit package

Abstract: A decoupling scheme is presented which is well suited for use with any type of integrated circuit package. In accordance with the present invention, a flat decoupling capacitor is attached directly to the top of an IC die and is electrically connected to the IC by means of raised conductive bumps provided either on the surface of the decoupling capacitor or on the IC die surface. These conductive bumps interconnect the internal electrodes of the capacitor to the power and ground circuits of the IC. The resulting decoupling scheme provides a decoupling loop with an inductance which is significantly lower than previously disclosed decoupling loops.

MOSFET multiplying circuit

Abstract: The invention relates to a voltage multiplying circuit having several stages, with each stage having a pumping capacitor and several MOS switching transistors. The switching transistors are so controlled by clock signals that the charge of a pumping capacitor of one stage is transferred to the pumping capacitor of the following stage. Operation of a circuit of this type with operating voltages substantially lower than 5 V entails considerable drawbacks. In accordance with the invention, therefore, each stage of a voltage multiplying circuit of this type is fitted with an additional transistor and an additional correction capacitor. As a result, the circuit in accordance with the invention is suppliable with an operating voltage of 2 V, for example. In another circuit arrangement, the transistors of the last two or three stages of the voltage multiplying circuit are of one conductivity type, while the transistors of the previous stages are of the opposite conductivity type. The last stages do not need a correction capacitor.

Adaptable current mirror

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that then input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

Molded integrated circuit package incorporating thin decoupling capacitor

Abstract: A decoupling scheme which is particularly well suited for use with molded integrated circuit packages incorporating lead frames is presented. In accordance with the present invention, a thin decoupling capacitor is used which is comprised of a ceramic or like substrate having printed or otherwise applied thereon conductive layers, dielectric layers (e.g., glass/ceramic dielectric paste or dielectric sol-gel) and protective layers. Mounted on this thin capacitor is an integrated circuit chip. This thin capacitor/IC chip assembly is attached directly to the IC lead frame and thereafter encapsulated within the molded package resulting in a decoupling scheme which is internal to the molded IC package. Printed conductors on the thin capacitor's ceramic substrate are attached to appropriate fingers of the lead frame by welding, soldering or the like to effect strong mechanical and electrical contact.

High voltage charge pumps with series capacitors

Abstract: A charge pump circuit is provided comprising a MOS capacitor, a capacitor ("series capacitor") connected in series, a MOSFET diode, and a voltage clamp connected to the common node of the MOS capacitor and the series capacitor. A number of these charge pump circuits may be cascaded to form a multi-stage charge pump circuit. Each charge pump circuit may attain output voltage higher than the oxide breakdown voltage of each individual MOS capacitor. This charge pump circuit can also operate under low voltage power supply conditions.

Low inductance side mount decoupling test structure

Abstract: An integrated circuit test structure is comprised of a stacked substrate MLC space transformer (5). A top surface of an interface substrate (12) is employed for decoupling capacitor (36) placement. The top surface has metal conductors (20) exposed thereon for terminating power supply buses from a tester (1). Individual layers of a personalization substrate (14) are fabricated to redundantly extend internal power plane metalization (22) to the sidewalls. Redundant pads (26) are placed on each personalization layer to increase the surface area for side mount contact. Metal pads (18) are deposited over the exposed sidewall metal for forming a sidewall contact to the power planes within the personalization substrate. The personalization substrate is joined to the upper surface of the interface substrate and the sidewall contacts are conductively coupled by conductive members (40) to the interface substrate metal conductors (20), thereby providing a low inductance, low resistance DC path from the tester to a device under test (4). The decoupling capacitors are electrically coupled to the metal lines in close proximity the personalization substrate thereby minimizing the associated lead inductance and maximizing the effectiveness of the decoupling capacitors.

Packaged integrated circuit with in-cavity decoupling capacitors

Abstract: An integrated circuit package is disclosed which has decoupling capacitors mounted within the cavity. A first embodiment has a thin-film capacitor mounted to the die attach of the header, with a first wire bond connecting the top surface to a lead finger of the header, and with a second wire bond connecting the top surface to the semiconductor chip mounted in the package. A second embodiment allows for decoupling of the power supply to a reference voltage other than that of the substrate, by providing a stacked capacitor where the top capacitor has a smaller cross-sectional area than the lower capacitor. Bond wires connect the top surface of the top capacitor to a first power supply lead, such as V cc , and to the V cc bond pad of the chip. The top surface of the lower capacitor, and consequently the lower surface of the top capacitor, are connected by bond wires to the reference supply (V ss ) lead of the package and bond pad of the chip.

Integrated circuit package having an internal cavity for incorporating decoupling capacitor

Abstract: A decoupling scheme is presented which is particularly well suited for use with integrated circuit packages having internal cavities for receiving an integrated circuit chip such as Pin Grid Array (PGA) packages, ceramic dual-in-line packages, ceramic flat packs and ceramic leadless chip carriers. In accordance with the present invention, a decoupling capacitor (which preferably comprises a very thin high capacitance layer made by a thick film or thin film process sandwiched between an inner and outer electrode layer) is positioned within the internal cavity of an integrated circuit package such as a PGA package and electrically connected to the IC chip within the cavity. In a particularly preferred embodiment, the decoupling capacitor has a novel configuration for improved heat transfer. This novel configuration includes a pair of parallel plate electrodes wherein the upper electrode has extended flaps which wrap around the top surface of the decoupling capacitor.

Device for electromagnetic static and voltage suppression

Abstract: A device for suppressing electromagnetic static and voltage surges induced on radio frequency transmission cables is disclosed. The device comprises a blocking capacitor connected to prevent the conduction of DC currents but to permit the transmission of radio frequency signals. An inductor coil is connected between one side of the capacitor and ground. The inductor coil is of a value that blocks conduction of radio frequency signals but allows static and low frequency DC voltage surges to be conducted to ground. A gas discharge unit is also connected from the same side of the capacitor to ground. The discharge unit is a secondary discharge device that only operates when the transient speed and magnitude of the surge is sufficient to cause a back emf to develop across the inductor coil above a predetermined limit. The gas discharge unit assures that the capacitor is not damaged by the back emf. A resistor is connected between the other side of the capacitor and ground to discharge any DC voltage developed on the other side of said capacitor.

Power converter for a switched reluctance motor

Abstract: Power conversion apparatus (10) for an n-winding switched reluctance motor (M). A rectifier circuit (12) rectifies line voltage supplied to the motor. A switching circuit (14) supplies, at any one time, electrical energy to the motor winding most capable of converting it to mechanical work. A storage capacitor (C1) stores any unconverted portion of the energy and returns it to the winding during subsequent cycles. The switching circuit provides a substantially long conduction period 2 (θ) for supplying electrical energy to the motor during each line voltage cycle. This permits use of a substantially smaller energy storage capacitor and results in a higher input power factor for circuit operation. Circuits for precharging the storage capacitor are eliminated. The switching circuit is capable of more modes of operation than previous circuits, while using fewer components, and therefore provides a lower cost design.

Motor vehicle power supply device

Abstract: A motor vehicle power supply device includes an alternator drivable by an engine mounted on a motor vehicle, a battery chargeable by electric energy generated by the alternator, a capacitor connected to the alternator and the battery, and a charging speed varying circuit arrangement connected between the capacitor, and the alternator and the battery, for varying the speed at which the capacitor is charged. The charging speed varying circuit arrangement is controlled to vary the speed at which the capacitor is charged, depending on the operating condition of the motor vehicle.

Capacitive fluid level sensor

Abstract: A linear compensated capacitive fluid-level sensing device includes three capacitors. A measurement capacitor is positionable during use to receive a fluid. A compensation capacitor is submerged in the fluid so that the fluid fills the space between the electrodes. An offset capacitor has a capacitance equivalent to the capacitance of the measurement capacitor when only air exists between the measurement electrodes. Charge applied to each of the three capacitors is discharged to an associated differential amplifier through a respective switch when the capacitors are disconnected from a charging voltage supply. The offset amplifier generates an inverted output current that is applied to the discharge currents of the measurement and compensation amplifiers. The compensation amplifier output gates a frequency-controlled oscillator that in turn controls the switches.

Power supply system for turbocharger with rotary electric machine

Abstract: A power supply system for supplying electric energy to a rotary electric machine coupled to a rotatable shaft of a turbocharger for supercharging an engine includes a battery for supplying electric energy to the rotary electric machine, and a capacitor connected parallel to the battery through a switching control device. The capacitor is charged with electric energy from the battery at all times. When the engine needs to be revved up for quick acceleration, the switching control device is energized to supply electric energy stored in the capacitor, together with the electric power from the battery, to the rotary electric machine. Since the capacitor has a smaller internal resistance as compared with the battery, the capacitor can supply a large current to the rotary electric machine immediately after the accelerator pedal is deeply depressed for quick acceleration.

Switched capacitor interleaved forward power converter

Abstract: A DC-to-DC power converter topology utilizing parallel connected transformers in a buck switching configuration with each stage operated 180° out-of-phase, with the primary windings of the transformers sequentially feeding into a common filter capacitor. On each transformer, a secondary winding is switched to a load at the time the primary winding is shunted across the filter capacitor. The circuit provides dual inductor buck power stage operation while maintaining input-output isolation. Interleaved power processing provides continuous capacitance support for the output voltage produced by the power supply.

Signal level control circuit having alternately switched capacitors in the feedback branch

Abstract: A circuit for controlling the amplitude of video signals includes a control circuit which contains a first capacitor. For each image pulse, a charge which corresponds to the amplitude of the generated video signal during a prior frame cycle is stored in the first capacitor. During the frame flyback pulse, this charge is transferred to a second capacitor by means of a switch. The second capacitor's voltage serves as a control voltage for the video signal. After the charge is transferred to the second capacitor, the first capacitor is discharged.

Back-to-back capacitor charge pumps

Abstract: A charge pump circuit is provided comprising a first MOSFET capacitor ("pumping capacitor"), two other MOSFET capacitors ("back-to-back capacitors") connected together with a common junction of the back-to-back capacitor in series with the pumping capacitor, a voltage clamp connected to the common node of all three MOSFET capacitors, and a diode for output of the charge pumped. A number of these charge pump circuits may be cascaded to form a multi-stage charge pump circuit. Each charge pump circuit may attain output voltage higher than the oxide breakdown voltage of each individual MOS capacitor. This charge pump circuit can also operate under low voltage power supply conditions.

Lamp starting circuit

Abstract: A hot restart circuit includes a storage capacitor and SCR connected across a tapped portion of a ballast with a breakdown device to start the SCR. A charging circuit for the storage capacitor includes a diode, pumping capacitor and choke in series from the ballast tap to the AC line and a further diode interconnecting the capacitors. The pumping capacitor increases the charge on the storage capacitor in a step-wise fashion until the breakdown voltage is reached, whereupon starting pulses are applied to the lamp.

Active matrix display device having additional capacitors connected to switching elements and additional capacitor common line

Abstract: An active matrix display device having low resistance additional capacitor common lines and additional capacitors in which each of the additional capacitors has a first electrode connected to a switching element and a second electrode connected to the additional capacitor common line, and the additional capacitor common line is made of the same material as the signal lines, so that the possibility of signal delay on the additional capacitor common lines is reduced

High charge capacity focal plane array readout cell

Abstract: A high charge capacity readout cell in a hybrid focal plane detector array on a complementary metal oxide semiconductor integrated circuit chip. An input transistor that provides a buffer for the detectors of the array, couples to a source of bias voltage, which controls the operation of the transistor. An integrating capacitor uses a variable source of terminating voltage to increase the amount of charge it integrates. A read signal causes an output transistor to read the charge from the capacitor to a readout line and to initialize the capacitor. The termination voltage of the integrating capacitor is changed during the time that the detector current is integrated, thus increasing the change in total voltage across the capacitor. This allows a greater amount of charge to be integrated with the capacitor which improves the signal-to-noise ratio of the focal plane array.

Ionization current detector device for an internal combustion engine

Abstract: An ionization current detector for detecting the combustion states of an internal combustion engine is disclosed, which comprises: a high voltage generation circuit means, including a series circuit of a resistor, a diode, a capacitor, and a Zener diode, coupled across the output terminal of the ignition coil and the ground; diodes coupled across the peripheral terminals of the distributor and a negative terminal of the capacitor; and a current detector circuit including a resistor coupled across the positive terminal of the capacitor and the ground and a voltage divider for detecting the amount of the ionization current. An additional Zener diode is coupled in parallel with the capacitor to limit the voltage across the capacitor. The whole detector is incorporated into a single unit mounted to the distributor cap.

DC-DC converter and a computer using the converter

Abstract: In order to provide miniaturization and increased-frequency operation of a DC-DC converter used with a computer, etc., a capacitor is connected in parallel with a switching element when the switching element is turned off to reduce turn-off loss. When the switching element is turned on, the capacitor and a DC power source are connected in series to supply the energy stored in the capacitor to a load circuit to result in a high initial voltage being applied across the load circuit.

Electric power generating system with active damping

Abstract: The problem of filtering DC power on a DC bus (46) in an electrical power generating system (10) is resolved using an active damper circuit (44). The active damper circuit (44) comprises a capacitor (CD) and a switching circuit (70) for alternately switching the capacitor (CD) into and out of parallel relationship with the DC bus (46).

Fault indicator having liquid crystal status display

Abstract: A fault indicator for indicating the occurrence of a fault current in a monitored electrical conductor of an AC power distribution system utilizes a liquid crystal display having independent "F" and "N" display elements. A rectifier circuit capacatively coupled to the conductor charges a first capacitor in the presence of voltage on the conductor. A second capacitor is connected to the first capacitor by a first reed switch in magnetic communication with the conductor. Upon occurrence of a fault current the reed switch closes and a portion of the charge on the first capacitor is transferred to the second capacitor, which is connected to the "F" display segment electrodes of the liquid crystal display to cause an "F" to be displayed. The fault indication can be reset either by the slow discharge of the second capacitor, or by discharging the second capacitor through a second reed switch manually actuated by a magnetic reset tool from outside the fault indicator housing. The "N" display segment electrodes are capacitively coupled to the monitored conductor and system ground to provide an "N" display indicating that voltage is present on the conductor.

Variable capacitance capacitor array

Abstract: A capacitor array provides a variable capacitance, having FET's as respective switching elements (10, 11, 12) for switching each capacitor (20, 21, 22) in the array on and off, and means (8) for controlling switching of the switching elements to switch selected ones of the capacitors on, characterised in that the control means are arranged to co-operate with voltage generation means (7) so as to supply to a control electrode of each switching element for switching on a selected said capacitor a voltage which causes the impedance provided by said switching element to change between multiple levels.