Showing papers on "Decoupling capacitor published in 1997"

Switched capacitor system for automatic series battery equalization

Abstract: A clocked switched-capacitor circuit can exchange charge between adjacent batteries in a series string. This exchange drives all batteries to identical voltages, without regard to component values, battery technology, or state of charge. This equalization process can proceed while the batteries are in use or under charge, or separately. Transformer-based and transformerless implementations are given, and results of experimental tests are provided. The process is much faster and less stressful than the conventional approach, and is simpler than some active approaches.

Power supply noise analysis methodology for deep-submicron VLSI chip design

Abstract: This paper describes a new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors.Based on an integrated package-level andchip-level power bus model, and a simulated switching circuitmodel for each functional block, this methodology offersthe most complete and accurate analysis of Vdd distributionfor the entire chip. The analysis results not only providedesigners with the inductive ΔI noise and the resistive IRdrop data at the same time, but also allow designers to easilyidentify the hot spots on the chip and ΔV across the chip.Global and local optimization such as buffer sizing, powerbus sizing, and on-chip decoupling capacitor placement canthen be conducted to maximize the circuit performance andminimize the noise.

Energy Storage Characteristics of a Piezo-Generator using Impact Induced Vibration

Abstract: This paper presents theoretical and experimental considerations of the energy storage characteristics of a piezoelectric generator developed previously by the authors. In this paper, the oscillating output voltage induced by mechanical impact via the piezoelectric effect is rectified, and the electrical energy is stored in a capacitor. The effect of the capacitance of the capacitor and the initial voltage is investigated using an equivalent circuit model. A maximum efficiency over 35% has been achieved with a prototype generator.

Small current detector circuit and locator device using the same

Abstract: The improved small current detector circuit and locator device each include a first and a second capacitor, a pulse drive circuit which drives one terminal of each capacitor by a pulse signal and charges and discharges the capacitors in synchronism with the rise and fall of the applied pulse so as to generate a first and a second detection signal at the other terminal of each capacitor. A current generator circuit receives the first and second detection signals and generates a current representing the difference between the levels of said signals. An integrator circuit integrates the output current from the current generator circuit. At least one of the first capacitor or second capacitor is provided in a detection portion of the detector circuit or locator device.

Super capacitor battery clone

Abstract: An aircraft electrical supply bus supplementing arrangement in which electrical energy is stored in a large capacitor and energy flow between the capacitor and the bus is controlled by a bi-directional electrical converter circuit of the switched inductance type. The varying terminal voltage of the energy storing capacitor, a super capacitor, is coupled to the relatively fixed voltage of the aircraft supply bus by way of the voltage changing capability of the converter circuit switched inductance. Current flow levels in this inductance are controlled with a negative feedback regulator circuit. Energy storage efficiency in the converter is enhanced with respect to weight and physical size of the capacitor element by ability of the converter circuit to accept a widely varying input voltage while generating a relatively constant output voltage. Suppression of electrical transients and improved regulation of voltage on the aircraft energy supply bus especially at distal and bus impedance-isolated locations are achieved.

Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors

Abstract: A ball grid array to integrated circuit interconnection. The interconnection includes a ball grid array substrate having a first surface and a second surface. The first surface comprising a plurality of substrate interconnection conductive pads. A power supply via connects a power supply conductive pad of the first surface to a first conductive area on the second surface. A ground via connects a ground conductive pad of the first surface to a second conductive area on the second surface. A decoupling capacitor connected between the first conductive area and the second conductive area. The interconnection further comprises an integrated circuit comprising a plurality of integrated circuit conductive pads. A plurality of smaller solder balls interconnect at least one of the integrated circuit conductive pads to at least one of the substrate interconnection conductive pads. A circuit board substrate is electrically interconnected by larger solder balls to the ball grid array substrate.

Higher-efficiency cold-cathode fluorescent lamp power supply

Abstract: A switched-mode power supply for energizing a cold-cathode fluorescent lamp ("CCFL") includes a first semiconductor switch connects in series with a primary winding of a step-up transformer. The primary winding and a secondary winding, having many more turns than the primary winding, are disposed about a transformer core which has a linear magnetic permeability. A series connected second semiconductor switch and capacitor connect in parallel with the transformer's primary winding. A controller circuit transmits signals to turn the switches on and off. The controller circuit turns the first and second semiconductor switches on and off at a frequency that is higher than a resonant frequency of a parallel resonant circuit formed by the primary inductance of the transformer and capacitance of the capacitor. A decoupling capacitor connects in series to a first end of the transformer's secondary winding. A second terminal of the decoupling capacitor and a second end of the secondary winding provide ac power output terminals for the switched-mode power supply across which a CCFL may be connected.

Capacitive PCB with internal capacitive laminate

Abstract: An in situ method for forming a bypass capacitor element internally within a PCB including the steps of arranging one or more uncured dielectric sheets with conductive foils on opposite sides thereof and laminating the conductive foils to the dielectric sheet simultaneously as the PCB is formed by a final lamination step, the conductive foils preferably being laminated to another layer of the PCB prior to their arrangement adjacent the dielectric sheet or sheets, the dielectric foils even more preferably being initially laminated to additional dielectric sheets in order to form multiple bypass capacitive elements as a compound subassembly within the PCB A number of different dielectric materials and resins are disclosed for forming the capacitor element A dielectric component in the capacitor element preferably includes dielectric material and thermally responsive material, the thermally responsive material either forming a carrier for the dielectric material or formed as two separate sheets on opposite sides of a sheet of the dielectric material

Sample-and-hold circuit for a switched-mode power supply

Abstract: A sample-and-hold circuit is provided for a switched-mode power supply of the type having a transformer with a primary winding, an auxiliary winding and a secondary winding, with a switching transistor coupled in series with the primary winding and a sample-and-hold capacitor for storing a voltage proportional to an output voltage of the auxiliary winding and coupled to a controlled terminal of the switching transistor in a feedback loop which normally operates in a closed-loop mode for switchably regulating the power supply. To prevent the feedback loop from being driven to an open-loop or "stuck" mode of operation, a discharge capacitor is provided which is switchably coupled in parallel with the sample-and-hold capacitor to discharge excess voltage from the sample-and-hold capacitor and thereby restore the feedback loop to its normal closed-loop operating mode.

Super capacitor charging

Abstract: An aircraft electrical energy supply bus supplementing arrangement based on large capacitor or super capacitor storage of electrical energy for bus supplementation. Supplying of bus energy to the large capacitor is addressed in the invention. In this supplying energy is removed from the aircraft bus during quiescent conditions under the control of a energy coupling circuit which has a plurality of different energy removal rates, rates which are selected in response to the yet needed amount of capacitor charging and in a time-constant-controlled manner. Feedback control of this charging time constant selection is employed along with passive electrical device dissipation of major fractions of the time constant apparatus energy losses.

Capacitor with dual electric layer

Abstract: The present invention relates to a capacitor with a dual electric layer, wherein one electrode of said capacitor is made of a carbon-based porous material while the other electrode is made of a material containing lead sulphate. The capacitor of the present invention exhibits improved specific characteristics and has a lower cost.

New current-controlled PWM rectifier-voltage source inverter without DC link components

Abstract: The voltage-source inverters are normally equipped with an electrolytic capacitor in their DC link, the electrolytic capacitor has several disadvantages such as increasing size, limiting converter life and reliability. Therefore several approaches for removing the DC link capacitor have been studied. This paper proposes a new voltage source inverter without DC link components, whose rectifiers are controlled by suitable current feedback to adjust near-sinusoidal AC source current waveforms at unity power factor. The calculated characteristics are described for a 0.75 kW induction motor driven by this inverter.

Method of making large value capacitor for SOI

Abstract: Large capacitance, low-impedance decoupling capacitors in SOI and their method of fabrication. A high conductivity trench substrate contact is made adjacent to the capacitor by removal of insulator lining the capacitor by use of an extra mask thereby making a substrate contact when the trench is filled with doped polysilicon. The inventive process is compatible with and easily integrated into existing SOI logic technologies. The SOI decoupling capacitors are formed in trenches which pass through the silicon and buried oxide layers and into the underlying silicon substrate.

Amplifier circuit with reduced DC power related turn-on and turn-off transients

Abstract: An amplifier circuit with improved turn-on and turn-off transient operation includes a differential amplifier and a selectively variable reference generator for controlling the amplifier output during circuit turn-on. The amplifier has differential inputs which are driven by a reference voltage from the reference generator and a single-ended input signal. During circuit turn-on, the selectively variable reference voltage, generated by charging the bypass capacitor with a constant current source, charges in a linear manner from ground potential toward its final value of, typically, half of the power supply voltage. During circuit turn-off, the bypass capacitor is discharged with a constant current source in a linear manner toward ground potential. This allows improved turn-on and turn-off transient operation to be realized, e.g. reduced "pops" and "clicks" upon circuit turn-on and turn-off, while giving the user increased flexibility in selecting the sizes of the reference voltage bypass capacitor and the input signal coupling capacitor.

Adjustable gain active pixel sensor

Abstract: An active pixel sensor. The active pixel sensor includes a photo-diode. The photo-diode conducting charge as a function of the intensity of light received by the photo-diode. The photo-diode includes a diode capacitance which collects charge conducted by the photo-diode which generates a photo-diode voltage. A switched capacitor is connected in parallel with the photo-diode when the photo-diode voltage drops below a pre-determined voltage potential. A capacitance of the switched capacitor adds to the diode capacitance when the switched capacitor is connected. The switched capacitor can be a gate capacitor. The active pixel sensor further includes electronic circuitry to allow a controller to sample the photo-diode voltage.

Overcurrent trip device

Abstract: An overcurrent trip device includes a capacitor 13 that stores power for driving a trip electromagnet 7, and a charging current generating means 18 that starts charging the capacitor 13 upon detection of an overcurrent and that completes the charging of the capacitor 13 until a trip control circuit 5 outputs a trip signal. The operation of the trip electromagnet 7, which is driven with the charges of the capacitor 13 by causing a thyristor 12 to be turned on by the trip signal, is continued until the charges of the capacitor 13 are lost, and even after the power supply from a rectifying circuit 4 is stopped due to the opening of a circuit breaker 8, it is made impossible to reset and re-close the circuit breaker 8 for a predetermined time.

Method and apparatus for checking insulation of ungrounded power source

Abstract: An apparatus includes an insulated first switching element and a capacitor which are connected in series between one of positive and negative main circuit wirings connected to an ungrounded power source and a ground potential section (vehicle body); a second switching element with one terminal thereof connected to a junction point of the first switching element and the capacitor; switching element control device for selectively closing the first switching element for a predetermined time so as to charge the capacitor and for closing the second switching element so as to discharge the capacitor while the first switching element is opened; device for detecting the electric charge accumulated in the capacitor; and device for determining the insulation between the other of main circuit wirings and the ground potential section in accordance with the detected amount of charge.

Common source transistor capacitor stack

Abstract: New arrangement of a vertical field effect transistor and a capacitor together forming a memory cell which in turn may be the basic building block of a memory chip, such as a very high density DRAM. The capacitor's first electrode is connected to the drain of the transistor. The transistor's source is connected to the sources of other transistors, the gate is connected to a word line, and the second electrode of said capacitor is connected to a bit line.

Application of system-level EM modeling to high-speed digital IC packages and PCBs

Abstract: A system-level electromagnetic (EM) modeling tool combining a three-dimensional (3-D) full-wave finite-element EM-field analysis tool and a time-domain electric-circuit simulator is developed and applied to various geometries such as multilayer printed circuit boards (PCBs), signal lines embedded in a PCB or package, and split power-distribution network. Since the signal integrity is a primary concern of high-speed digital circuits, the noise distributions on various circuit planes are evaluated from the analysis. These noise distributions, often called voice maps, are utilized to identify the location of the major source of simultaneous switching noise (SSN). This information can eventually be adapted for optimum placement of decoupling capacitors to minimize the noise fluctuations on the various circuit planes on an entire PCB.

Solid-state imager having capacitors connected to vertical signal lines and a charge detection circuit

Abstract: A signal charge in an amplifying type solid-state imaging device of a capacitor load charge system can be detected efficiently. The amplifying type solid-state imaging device is composed of a plurality of pixel transistors, a load capacitor for accumulating signal charges of an amount corresponding to light incident on the pixel transistor, an operational amplifier having a first input terminal connected with the load capacitor element and a second input terminal to which a bias voltage is applied, a detection capacitor element connected in parallel to the operational amplifier and a reset switch for resetting the detection capacitor element.

Capacitance or capacitance variation detection circuit

Abstract: The circuit has a clock generator (1) controlling a switching contact (2) coupled at its input (7) to one electrode (6) of the capacitive component or circuit, a storage capacitor (3), a voltage source (4) and an evaluation stage (5). One output (9) of the switching contact is coupled to a reference potential (10), its second output (11) coupled to one electrode of the storage capacitor which is coupled to the reference potential at its second electrode. The first electrode of the storage capacitor is coupled to the voltage source via a resistance network (8) and to the evaluation stage.

Current-to-voltage integrator for analog-to-digital converter, and method

Abstract: An integrating circuit includes an operational amplifier and an integrating capacitor which is decoupled from the output of the operational amplifier and precharged to a positive reference voltage before each integration cycle. During each integration cycle the operational amplifier output decreases from the reference voltage toward but not below ground. This allows the operational amplifier to be included as a front-end integrator to a delta-sigma analog-to-digital converter that is powered only by a single power supply. In the described embodiment, the output is coupled to an input of an auto-zeroing stage which provides negative feedback to stabilize the operational amplifier when the integrating capacitor is disconnected during precharging and a bandwidth control input which couples a larger compensation capacitance to reduce the bandwidth during integration to reduce RMS noise. In the described embodiment, a correlated double sampling capacitor is discharged to zero while the integrating capacitor is precharged and kT/C error and charge injection error voltages of opposite polarity are stored on both the integrating capacitor and the correlated double sampling capacitor. The correlated double sampling capacitor is switched into the feedback of the operational amplifier in series with the integrating capacitor to automatically cancel the error voltages and present a more accurate input to the delta-sigma analog-to-digital converter.

Decoupling capacitor network for off-state operation

Abstract: Decoupling capacitors are activated by high current impulses that occur due to electrical over stress or electrostatic discharge, which occurs when the chip is powered off with no additional control signal or feedback elements. The high current or high voltage impulse is used to activate a rise time network, which turns on an electric switch, enabling the capacitor network. The basic circuit can be modified to address the situation where a failed decoupling capacitor needs to be switched out. In this modification, there is in addition to the three basic elements listed above, a feedback element connected between the decoupling capacitor and the switch. This feedback element operates to turn the electronic switch off when the decoupling capacitor is leaky. A further modification of the basic invention allows the decoupling capacitor to be used as a decoupling transistor during chip operation and as a capacitor during electrostatic discharge (ESD) testing or an ESD event.

Impedance-matching network

Abstract: A high efficiency radio frequency (RF) impedance matching network containing an "L-type" inductor-capacitor (LC) circuit where the capacitor is a variable capacitor coupled from an input port to ground and the inductor is a variable inductance inductor coupled from the input port to an output port. A blocking capacitor is provided between the inductor and the output port and a ceramic capacitor is coupled in parallel across the variable capacitor. The impedance match is tuned by physically adjusting tuning elements of both the inductor and capacitor. The variable inductor contains an improved inductor tuning element that optimizes current flow in the tuning elements and inductor. To further improve the efficiency of the matching network, the assembly uses an improved enclosure interior finish and various circuit optimization techniques that reduce contributions to match loop resistance.

Optional on chip power supply bypass capacitor

Abstract: An integrated circuit includes main power busses located on the next to the top most level of metal and a top level of metal separated from the main power busses by a thin dielectric. The top most level metal is connected to one of the power buses either through bond wires or through contacts. This structure provides a distributed bypass capacitance between the power buses thus stabilizing the power bus voltage within the integrated circuit. Furthermore, this capacitance structure can be optional and can be made with one or two masking steps.

Decoupling capacitor structure distributed above an integrated circuit and method for making same

Abstract: The present invention describes the use of large thin film (TF) capacitors having capacitance C made in a separate set of TF layers ABOVE the Si and wiring levels of an integrated circuit (IC). This C is very large. This invention describes a two-level IC architecture in which a metal/insulator/metal (MIM) capacitor structure comprises the upper level, and CMOS logic and memory circuits made in the Si wafer substrate comprise the lower level. The added thin film capacitance serves to stabilize the power supply voltage at a constant level during GHz IC operation.

Cross-coupled capacitors for improved voltage coefficient

Abstract: A capacitor having a low voltage coefficient, even though one electrode is a semiconductor and one is a metal, is described. Two parallel plate capacitors are formed side by side and then cross-connected. The bottom plate of one of the capacitors is connected to the top plate of the other capacitor, and vice versa. This arrangement causes the two capacitors to be polarized in opposite directions at all times so that the individual voltage coefficients cancel each other and give the combined structure a value that is about 2 ppm V. A process for manufacturing this capacitor is also described.

In-rush current reduction circuit for boost converters and electronic ballasts

Abstract: An electronic power supply circuit (50) that includes a rectifying circuit (14), a boost converter (16), an in-rush current reduction circuit (52), and a bulk capacitor (18). The in-rush current reduction circuit (52) includes an in-rush current limiting resistor (54) and a bypass capacitor (56) that are connected in parallel with each other. An improved version of the in-rush current reduction circuit (52) includes a bypass diode (58) connected in parallel with the in-rush current limiting resistor (54) and bypass capacitor (56) which is oriented to provide a path for current flowing out of bulk capacitor (18). One particular application of the disclosed circuit is for use in an electronic ballast for fluorescent lamps.

Fixed/switched type shunt capacitor planning of distribution systems by considering customer load patterns and simplified feeder model

Abstract: A shunt capacitor planning strategy to reduce system resistive losses and improve voltage profile for distribution feeders has been proposed. The objective function consists of peak load loss, energy loss and shunt capacitor cost, while operational constraints such as bus voltage profile and real shunt capacitor size are considered throughout the overall solution procedure. A three-phase load flow program, which accounts for the mutual coupling effect between conductors, unbalanced loading among phases, and feeders with multiple lateral branches, is applied to enhance the computer simulation. The simplified feeder model has been developed to derive the equivalent circuit of minor lateral branches so that the data processing work for the feeder configuration can be reduced efficiently. Besides, the customer load patterns as well as the feeder load curve for various seasons are derived so that the section load behaviour can be estimated more realistically. According to the reactive load duration curve of the feeders studied, the capacitor operation strategy by considering both fixed and switched shunt capacitors is developed to determine the proper size, location and switching time of capacitors to enhance the system operation efficiency. Two practical feeders in the Taipower (Taiwan Power) distribution system are selected for demonstration to show the effectiveness of the proposed method. Capacitors with optimal size are installed according to the schemes derived by computer analysis. Field tests are then performed and the energy loss reduction as well as the improvement of power quality of the test feeders can be justified.

Packaging and power distribution design considerations for a Sun Microsystems desktop workstation

Abstract: The power distribution system will become an increasingly important package design consideration for computer systems such as the Sun Microsystems desktop workstation, at least as important as simultaneous switch. Power distribution impedance is controlled by the switching power supply, bulk capacitance, ceramic capacitance and power plane properties at various portions of the frequency spectrum. A major concern with package power is resonance between chip capacitance and package inductance. The key parameters for package power are the core power supply loop inductance and the inductance and resistance used to connect any decoupling capacitors on the package. Decoupling capacitors on the package can be used but they will not be effective unless the connections to them are specially designed using aggressive technologies.