Showing papers on "Decoupling capacitor published in 1998"

Chip capacitors and chip capacitor electromagnetic interference filters

Abstract: An electromagnetic interference (EMI) filter capacitor assembly is provided for shielding and decoupling a conductive terminal pin or lead of the type used, for example, in an implantable medical device against passage of external interference signals. The EMI filter is constructed of relatively inexpensive ceramic chip capacitors which replace relatively expensive feedthrough capacitors as found in the prior art. The chip capacitors are mounted directly onto a hermetic feedthrough terminal in groups of two or more which vary in physical size, dielectric material and capacitance value so that they self-resonate at different frequencies. This "staggering" of resonant frequencies and direct installation at the hermetic terminal provides the EMI filter with sufficient broadband frequency attenuation. In one preferred form, multiple chip capacitor groupings are mounted onto a common base structure, with each capacitor grouping associated with a respective terminal pin. In another preferred form, a non-conductive substrate is provided with metalized circuit traces to better accommodate the mounting of the chip capacitors. Additionally, novel chip capacitor geometry/termination-metallization is provided which significantly reduces the internal inductance of the capacitor to improve its high frequency performance as an EMI filter. Such reduced inductance chip capacitor designs are readily adaptable to incorporate multiple electrically isolated active plate sets within a single monolithic casing.

A feedback linearizing control scheme for a PWM converter-inverter having a very small DC-link capacitor

Abstract: This paper addresses a control method of reducing the size of the DC link capacitors of a power converter-inverter system. The main idea is to utilise the inverter operation status in the current control of the power converter. Specifically, information on the load power is incorporated in synthesizing the converter current control input so that a proper DC voltage level is maintained. The authors describe the dynamics of load current and apply feedback linearization theory to obtain an input output linearized system. Theoretically, this control strategy is effective in regulating the DC voltage level even though the DC link capacitor is arbitrarily small and load varies abruptly. The superior performance is demonstrated through simulation and experiment. Experiment was performed with a 9 kW PWM power converter-vector inverter system having a 75 /spl mu/F DC-link capacitor.

Perovskite thin films for high-frequency capacitor applications1

Abstract: ▪ Abstract Perovskite, ferroelectric and paraelectric, thin films exhibit outstanding dielectric properties, even at high frequencies (>1 GHz). This feature makes films such as (Ba,Sr)TiO3 and Pb(Zr,Ti)O3 ideally suited for a wide range of capacitor applications, particularly decoupling capacitors and tunable microwave capacitors; the latter application has been fueled by the recent explosion in wireless communications. The successful implementation of these materials as high-frequency dielectrics requires a detailed understanding of both their processing and materials properties.

Chip capacitor electromagnetic interference filter

Abstract: An electromagnetic interference (EMI) filter capacitor assembly is provided for shielding and decoupling a conductive terminal pin or lead of the type used, for example, in an implantable medical device against passage of external interference signals. The EMI filter is constructed of relatively inexpensive ceramic chip capacitors which replace relatively expensive feedthrough capacitors as found in the prior art. The chip capacitors are mounted directly onto a hermetic feedthrough terminal in groups of two or more which vary in physical size, dielectric material and capacitance value so that they self-resonate at different frequencies. This "staggering" of resonant frequencies and direct installation at the hermetic terminal provides the EMI filter with sufficient broadband frequency attenuation. In one preferred form, multiple chip capacitor groupings are mounted onto a common base structure, with each capacitor grouping associated with a respective terminal pin. In another preferred form, a non-conductive substrate is provided with metalized circuit traces to better accommodate the mounting of the chip capacitors. Additionally, novel chip capacitor geometry/termination-metallization is provided which significantly reduces the internal inductance of the capacitor to improve its high frequency performance as an EMI filter.

Resonance and damping in CMOS circuits with on-chip decoupling capacitance

Abstract: Design of on-chip decoupling capacitance and modeling of resonance effects in the power supply network of CMOS integrated circuits is addressed. The modeling is based on mathematical limits proving that damping will be low, resulting in resonance unless careful design is used. Design strategies that reduce resonance are discussed. It is shown that an optimal parasitic resistor in series with the decoupling capacitor gives a maximum damping factor of 0.5 and practical values are within the range 0.3-0.4. Examples of digital circuits show that proper design of on-chip decoupling capacitance may reduce the number of bonding wires by an order of magnitude. The modeling and design suggestions are also applicable to mixed-mode circuits. In particular, sampled analog networks benefit with a potentially higher sampling rate if enhanced damping is introduced during design.

Method and system for detecting nonfunctional elements in an ink jet printer

Abstract: A method and system for detecting a nonfunctional element in an ink jet printhead is disclosed. The ink jet printer system includes: a switching power supply, coupled to the inkjet printhead, for supplying power to the printhead; an output capacitor, coupled to an output of the switching power supply, for storing a dc voltage therein; a bleed resistor, coupled in parallel to the output capacitor, for discharging current from the output capacitor; an output shifting circuit, coupled to the switching power supply, for shifting the dc voltage level across the output capacitor between a low state and a high state; and a sensor, coupled to the output of the switching power supply, for detecting when the switching power supply is switching, wherein an element of the printhead is tested by measuring a test current discharging from the output capacitor when the element is activated and comparing the measured test current with a reference current which discharges from the output capacitor through the bleed resistor. The method includes: supplying regulated power to the printhead; storing the regulated power in a capacitor so as to provide a dc voltage across the capacitor; shifting the dc voltage level stored in the capacitor between a low state and a high state; measuring a test current discharging from the capacitor when an element of the printhead is activated; measuring a reference current discharging from the capacitor through a bleed resistor, when no elements of the printhead are activated; and comparing the measured test current with the reference current.

Tunable-trimmable micro electro mechanical system (MEMS) capacitor

Abstract: A high Q MEMS capacitor that can be continuously tuned with a large tuning ratio or reversibly trimmed using an electrostatic force. The tunable capacitor has a master/slave structure in which a control voltage is applied to the master (control) capacitor to set the capacitance of the slave (signal) capacitor to which an RF signal is applied via a suspended mechanical coupler. The master-slave structure reduces tuning error by reducing the signal capacitor's surface area and increasing its spring constant, and may eliminate the need for discrete blocking inductors by electrically isolating the control and signal capacitors. The trimmable capacitor provides an electrostatic actuator that selectively engages a stopper with teeth on a tunable capacitor structure to fix the trimmed capacitance.

New generation of switched capacitor converters

Abstract: This paper presents a new generation of switched capacitor power converters. These new circuits use a reduced number of switches. The new family consists of three circuit topologies: double; inverting; and half the input voltage. All the switching devices are zero-current switching and hence the converter can operate at high switching frequency. The high switching current has also been reduced.

Switched capacitor current source for use in switching regulators

Abstract: In voltage regulator with a power switch to alternately couple and decouple an input voltage source to an output terminal at a switching frequency, a current supply provides a current that is proportional to the input voltage, the capacitance of a ramp capacitor, and a switching frequency To provide this current, a first capacitor is charged to a first voltage, the first capacitor is discharged to a second voltage through a variable current source at a rate which is controlled by a third voltage on a second capacitor, the first capacitor is connected to the second capacitor to bring the second capacitor to a fourth voltage to adjust the rate of flow of charge through the variable current source, and the first capacitor is recharged to the first voltage The rate of flow of charge through the variable current source controls the supply of current to the application

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Abstract: Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBM's CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Ink-jet printer, method and system compensating for nonfunctional print elements

Abstract: A method and system for detecting nonfunctional ink-jets and compensating for the nonfunctional ink-jets in an ink-jet printer (54). The ink-jet printer (54) includes a printhead (44) having a plurality of ink-jets (192), each ink-jet (192) being assigned to print respective dots on a respective raster line of a recording medium in accordance with a print mask (100), wherein when an ink-jet (192) is detected as being defective, at least a portion of said print mask is replaced with a replacement mask (500) such that one or more of the remaining ink-jets (192) of the plurality of ink-jets compensates for the detective ink-jet. The method includes: detecting when an ink-jet (192) is nonfunctional; and when an ink-jet is determined to be nonfunctional, replacing at least a portion of the print mask (100) with a replacement mask (500) such that one or more of the remaining ink-jets (192) of the plurality of ink-jets compensates for the nonfunctional ink-jet. In order to detect a nonfunctional element, e.g., an ink-jet, in the printhead, the ink-jet printer system of the invention further includes: a switching power supply (80), coupled to the ink-jet printhead (44), for supplying power to the printhead (44); an output capacitor (164), coupled to an output of the switching power supply (80), for storing a dc voltage therein; a bleed resistor (166) coupled in parallel to the output capacitor (164), for discharging current from the output capacitor (164); an output shifting circuit (164, 166, 172 and 174), coupled to the switching power supply, for shifting the dc voltage level across the output capacitor (164) from a low state to a high state; and a sensor (180), coupled to the output of the switching power supply (80), for detecting when the switching power supply (80) is switching, wherein an element of the printhead (44) is tested by measuring a test current discharging from the output capacitor (164) when the element is activated and comparing the measured test current with a reference current which discharges from the output capacitor (164) through the bleed resistor (166) where no element of the printhead (44) is activated. The method includes: supplying regulated power to the printhead (44); storing the regulated power in a capacitor (164) so as to provide a dc voltage across the capacitor; shifting the dc voltage level stored in the capacitor (164) from a low state to a high state; measuring a test current discharging from the capacitor (164) when an element of the printhead (44) is activated; measuring a reference current discharging from the capacitor (164) through a bleed resistor (166), when no elements of the printhead (44) are activated; and comparing the measured test current with the reference current.

Impedance matching device

Abstract: An impedance matching device includes a variable capacitor constituted by a non-linear dielectric thin film and an upper electrode disposed on a lower electrode formed on a substrate. The non-linear dielectric thin film is formed by a deposition, screen-printing, electroplating, or other technique, and changes its relative dielectric constant according to applied voltage. Therefore, the capacity of the variable capacitor is controlled and the impedance is matched, by simply controlling the applied voltage across the non-linear dielectric thin film. Consequently, the arrangement makes it possible to cut down the impedance matching device in size and cost, compared to an arrangement incorporating a capacitor and a coil for adjustment, effects a much simpler matching operation, and facilitates a manufacturing process.

Boost mode power conversion

Abstract: Boost Mode Regulator techniques are used to provide regulated a.c. or d.c. output from a.c. or d.c. sources. One embodiment involves regulation of the output of an a.c. source to provide a regulated d.c. voltage. The source inductance becomes part of the boost mode circuit, thus avoiding the losses associated with the addition of external inductors. When a three-phase alternator is the power source, the circuit comprises a six diode, three-phase rectifier bridge, three FET transistors and a decoupling capacitor. The invention involves shorting the output of the power source to allow storage of energy within the source inductance. During this time, the decoupling capacitor supports the load. When the short is removed, the energy stored in the inductances is delivered to the load. Because the circuit uses the integral magnetics of the source to provide the step-up function, the efficiency of the design can be quite high. In another embodiment, the leakage inductance of an isolation transformer is used to provide regulated a.c. or d.c. outputs from an a.c. source and to provide regulated a.c. or d.c. output from a d.c. source. Where a d.c. source is used, chopper circuits are used on the primary side of the transformer. The invention provides for regulation of the output voltage or for maintaining a power factor substantially close to unity.

Controlled shunt capacitor self-excited induction generator

Abstract: This paper proposes a new self-excited induction generator (SEIG) voltage regulation scheme. The proposed SEIG scheme utilizes the concept of a continuously controlled capacitor and is called the controlled shunt capacitor SEIG. Anti-parallel IGBT switches are used across the fixed excitation capacitors to regulate the voltage across a 7.5 hp induction generator. The experimental results and those obtained by simulation are similar. The experimental results prove that the controlled shunt capacitor SEIG maintains a constant terminal voltage over wide variety of loads and changes in speed, and hence is a reliable and cost-effective electric generator control system.

Multilayer capacitor with high specific capacitance and production process therefor

Abstract: A thin-film technology multi-layer capacitor with enhanced capacitance and/or reduced space requirement. The dielectric layers of which are alternately disposed between electrode layers on a substrate. Through alternate electrode layer connections, parallel interconnection of the individual capacitor layers is obtained. The result is that the individual capacitances are additive, while the temperature response can be optimized by a suitable choice or combination of different dielectric layers.

Method for fabricating a shielded multilevel integrated circuit capacitor

Abstract: A multilevel capacitor structure compatible with CMOS processing for use in switched capacitor circuits is disclosed. The capacitor structure has an associated parasitic capacitor which is placed in such a way so as to minimize the impact on the performance of a the switched capacitor circuit. The parasitic capacitor is formed between a first plate of the shielded capacitor and a diffusion well within a substrate. The diffusion well is connected to a quiet voltage reference source to isolate the shielded capacitor from noise present on the substrate. The shielded capacitor has a first plate that is fabricated from a first conductive material such as polycrystalline silicon or polycide, a second plate fabricated from a second conductive material such as a first level of metal on an integrated circuit, and a third capacitor plate fabricated from a second level of metal of an integrated circuit. The first plate and the third plate are connected to give a total capacitance given by the sum of capacitances between the first plate and second plate and between the second plate and third plate.

Ground and power patches on printed circuit board signal planes in the areas of integrated circuit chips

Abstract: The present invention is a multi-level printed circuit board (PCB) containing at least one power plane for conducting and distributing electrical power and at least one ground plane, spaced apart from the power plane, for providing and distributing an electrical ground. At least one integrated circuit chip is mounted on the printed circuit board. At least one signal plane is spaced apart from both the power plane and the ground plane, for conducting and distributing electrical signals from a first point to a second point. The signal plane(s) each have a portion or "patch" that is electrically isolated from signal traces in the remainder of the signal plane. The patches are placed in the area underneath the integrated circuit chip. The patches are connected, respectively, to the power plane or to the ground plane, for reducing effective inductance and input impedance. The multi-level PCB has one or more plated through hole vias for connecting the power or ground plane to a patch. Decoupling capacitors may be provided between the sets of plated through hole vias to further reduce input impedance.

Image pickup device and image pickup system using the same

Abstract: PROBLEM TO BE SOLVED: To reduce the numbers of temporary storage capacitors, stages of shift registers, common circuits, AGCs, and A/C converters by connecting a holding means shared by each photoelectric conversion part in a unit cell with a vertical output line and reading signals from the photoelectric conversion part to a signal holding means via the common circuit. SOLUTION: A signal storage structuring part 100 is provided with a capacitor Cs for storing the signal and a capacitor Cn for storing the noise, etc. The capacitor Cs for storing the signal and the capacitor Cn for storing the noise are provided to one vertical output line in parallel via transistors M1, M2. The signal stored in the capacitor Cs and the noise stored in the capacitor Cn are read on each horizontal output line by simultaneously turning transistors M3, M4 on by a horizontal shift register 13, and the signal is converted into a digital signal by removing the noise from it by a subtraction amplifier 10. Two kinds of capacitor Cn, Cs are provided per one vertical output line, two trains of photoelectric conversion signals are outputted by one vertical output line by a common amplifier and one capacitor is arranged per one train of photoelectric conversion parts.

Switched-capacitor sigma-delta analog-to-digital converter with input voltage overload protection

Abstract: A sigma-delta analog-to-digital converter includes an integrator having an input and an output and an integrator capacitor connected between the input and output. A switched-capacitor input circuit includes at least one input capacitor, an input sampling switching circuit and an input delivery switching circuit. The input sampling switching circuit includes at least one input sampling switch operable to connect the input capacitor to be charged by an input voltage at a sampling rate. The input delivery switching circuit includes at least one input delivery switch operable to connect the input capacitor to transfer charge to the integrator capacitor at a first transfer rate. A switched-capacitor feedback circuit is connected in a feedback path between the input and output of the integrator. The feedback circuit includes at least one feedback capacitor, a feedback sampling switching circuit and a feedback delivery switching circuit. The feedback sampling switching circuit includes at least one feedback sampling switch operable to connect the feedback capacitor to be charged by a feedback reference voltage at the sampling rate. The feedback delivery switching circuit includes at least one feedback delivery switch operable to connect the feedback capacitor to transfer charge to the integrator capacitor at a second transfer rate. The second transfer rate is a predetermined factor greater than the first transfer rate such that the sampled feedback reference voltage charge is transferred to the integrator capacitor at a greater rate than the transfer of the sampled input voltage charge to prevent modulator instability due to an input overload condition.

ESR and ESL of ceramic capacitor applied to decoupling applications

Abstract: Power distribution system noise affects computer product timing performance, signal integrity and electromagnetic interference. Between 1 MHz and 1 GHz, the primary means of reducing power distribution noise is with ceramic decoupling capacitors. To achieve a certain target impedance, it is important to characterize the ESR of ceramic decoupling capacitors, as this directly determines the number of capacitors required on a board. A new technique to extract ESR is described in this paper. Another factor which determines the capacitance value of decoupling capacitors is the ESL (equivalent series inductance) associated with capacitors mounted on a PCB. A study that compares the ESL of different pad layout geometries is also presented.

Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission

Abstract: Recently, electromagnetic interference (EMI) and radiated emission has become a major problem for high-speed circuit and package designers, and it is likely to become even severe in the future. However, until recently, designers of integrated circuit and package did not give much consideration to electromagnetic radiated emission and interference in their designs. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital system and boards. However, there has not been a systematic study to understand the effects of on-chip and off-chip decoupling capacitors on the electromagnetic radiated emission. In this paper, we report the simulation and the measurement results regarding the radiated emission due to the power/ground bounce. And we discuss the effects of the on-chip and off-chip decoupling capacitors to the power/ground bounce and the electromagnetic radiated emission. This circuit is simulated using HSPICE. Test ICs and printed circuit boards were designed and fabricated. Using a transverse electromagnetic (TEM) cell, the radiated electric field of the device under test (DUT) is measured. Combined placement of the on-chip and off-chip decoupling capacitor achieves more than 10 dB suppression of the radiated emission on the whole spectrum region. The design rule of the optimum placement of the decoupling capacitor was obtained.

Power conservation and management system for a self-powered electronic lock

Abstract: The charge on a capacitor is supplied by a manual generator in a self-powered lock. The capacitor retains a reduced level charge after completion of the operation of the electronic lock controls that may serve as a capacitor pre-charge. The pre-charge reduces the amount of manual input to the generator required. The drain of the electronic control circuitry on the capacitor is disconnected responsive to a microprocessor command at the completion of microprocessor operations. The disconnection may occur at a higher level of charge voltage on the capacitor when the control is from the microprocessor without having to wait for charge decay to reach a disconnect or power down level based on charge voltage level.

Reference voltage circuitry for use in switched-capacitor applications

Abstract: Circuitry for selectively sampling a reference voltage with a capacitor 403 includes a first switch 505a for selectively coupling capacitor 403 to a source of a first reference signal during a first operating phase and a second switch 505b for selectively coupling capacitor 403 to a source of a second reference signal during a second operating phase.

Integrated temperature sensor

Abstract: An integrated temperature sensor circuit (9) comprises two different current sources (14 and 15) multiplexed using switches (12 and 13) controlled by Clocks 1 and 2 having opposite phases into a bipolar transistor 11. V be is developed on capacitor (23) during the first clock phase and ΔV be is developed on capacitor (23) during the second clock phase. A second capacitor (27) is coupled between the input and output of an operational amplifier (25). The second capacitor (27) is discharged during the first clock phase and is charged during the second clock phase. Since ΔV be is dependent on temperature, the voltage at the output of the operational amplifier (25) is dependent on the temperature and the ratio of the two capacitors.

Integrated resonance circuit consisting of a parallel connection of a microstrip line and a capacitor

Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.

Developing a decoupling methodology with SPICE for multilayer printed circuit boards

Abstract: As CPU and bus speeds increase in high end workstation computer systems, signal integrity and EMI issues related to delta-I noise (caused by the current demands of the many fast switching devices on the PCB) require serious consideration during the design process. Historically, decoupling caps have been deployed "randomly" about the PCB in an attempt to mitigate this noise. However, as clock speeds increase beyond 500 MHz and rise times decrease to less than 300 psec, the design of power bus decoupling on multilayer boards requires close attention. Issues such as interplane capacitance, decoupling capacitor placement values and quantities, interconnect inductance as well as power bus resonances all need to be carefully manipulated and controlled in order to achieve the most cost effective and robust electromagnetically compatible products. In this paper a SPICE model is employed to examine the impedance of a typical power bus on a multilayer PCB. This impedance is calculated at numerous points (or nodes) around the board with respect to the noise sources and as a result the choice and quantity of decoupling capacitors as well as placement information and the resulting impact on the power supply impedance is evaluated.

Analysis and design on the reduction of DC-link electrolytic capacitor for AC/DC/AC converter applied to AC motor drives

Abstract: This paper presents the design of a three-phase quasi-direct AC/DC/AC converter with minimum energy storage in the DC-link capacitor. The proposed digital control scheme can achieve unity power factor, lower current distortion on the utility side, and fast response to DC-link voltage regulation. A power balancing control scheme is used to minimize the required DC-link capacitor. The design procedure of the proposed method, accompanied with given simulation results, has been described.

Low inductance power distribution system for an integrated circuit chip

Abstract: A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board. The decoupling capacitors have positive and negative electrodes are electrically coupled to the power and ground plated through holes respectively. The C4 power and ground bumps, the power and ground carrier vias, the power and ground carrier via subgroups, the power and ground solder balls, the contact pads, the power and ground plated through holes, and the positive and negative electrodes are arranged in anti-parallel tessellations to reduce the inductance of a loop circuit from the decoupling capacitors to the integrated chip circuit.

Integrated circuit device with integral decoupling capacitor

Abstract: A flat, thin decoupling capacitor is disposed inside an integrated circuit device in a coplanar relationship with a semiconductor chip and a bonding element When connected to the power and ground plane of a device substrate or in a leadframe device, the decoupling capacitor is positioned close to the semiconductor chip to substantially reduce ground bounce and crosstalk from the semiconductor chip When the decoupling capacitor is positioned to locate the semiconductor chip between itself and the device substrate or leadframe device, the decoupling capacitor shields electromagnetic interference from the semiconductor chip

Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices

Abstract: A trench capacitor structure suitable for use in a semiconductor integrated circuit device and the process sequence used to form the structure. The trench capacitor provides increased capacitance by including a capacitor plate consisting of textured, hemispherical-grained silicon. The trench capacitor also includes a buried plate to reduce depletion of stored charge from the capacitor.