Showing papers on "Decoupling capacitor published in 2000"

Classical equivalent circuit parameters for a double-layer capacitor

Abstract: As an emerging technology in the area of energy storage, the double-layer capacitor is a promising device for certain niche applications. The double-layer capacitor is a low voltage device exhibiting an extremely high capacitance value in comparison with other capacitor technologies of a similar physical size. Capacitors with values in excess of 1500 F are now available. In slow discharge applications on the order of a few seconds, the classical equivalent circuit for a double-layer capacitor, composed of a capacitance (C), an equivalent parallel resistance (EPR), and an equivalent series resistance (ESR), can adequately describe capacitor performance. The focus of this work is the determination of these parameters for four different capacitors from discharge data using standard laboratory equipment such as an oscilloscope. Capacitance values are calculated using a change in stored energy approach which allows determination of an initial capacitance, a discharge capacitance, and variations in capacitance with voltage. The sensitivity of ESR and capacitance to charge rate and initial charge voltage is also reported.

Circuit providing a control voltage to a switch and including a capacitor

Abstract: A circuit for providing a control voltage to a switch includes a capacitor, a first pair of switches for coupling the capacitor to an input voltage source and a second pair of switches for coupling the capacitor to the switch. The first pair of switches is controlled by a control signal in response to the voltage across the capacitor in order to prevent overcharging the capacitor beyond a first predetermined level. The second pair of switches is controlled by a second control signal in response to the voltage across the switch in order to replenish the capacitor voltage when the capacitor voltage falls to a second predetermined level. The first and second pairs of switches are closed during non-overlapping time intervals in order to isolate the switch from the input voltage source, thereby preventing switching transients from affecting the input voltage source and permitting the circuit to be used to drive a variety of switch types arranged in a variety of configurations.

Analysis of double-layer capacitors supplying constant power loads

Abstract: Double-layer capacitors are a recent technology based on the well-known electrochemical phenomenon of extremely high capacitance/unit area in an electrode-electrolyte interface and the high surface area achievable in activated carbon fibers. Capacitances are available in the range of a few farads to a few hundred farads. The energy stored in a bank of double-layer capacitors is related to the capacitance and the square of the voltage. The voltage of the capacitor bank decreases as energy is drawn by an external load. Seventy-five percent of the initial energy stored in the capacitor bank can be utilized if the voltage is allowed to decrease to one-half of its initial value. Because very few loads can tolerate a significant deviation in terminal voltage, a DC-DC converter can be connected between the capacitor bank and load to maintain a constant load voltage as the capacitor bank voltage decreases. A numerical procedure for computing the amount of time that a capacitor bank can supply a constant power load through a DC-DC converter is presented. The effective specific energy, which is defined as the ratio of the energy delivered to the load divided by the volume of the capacitor bank, can then be calculated and utilized to compare different bank configurations for a particular load.

On-chip decoupling capacitor optimization using architectural level prediction

Abstract: Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.

Apparatus for power factor control

Abstract: An apparatus for power factor control includes a capacitor for producing a substantially DC voltage and a switch for controlling the amount of energy stored in the capacitor in response to a switching signal. The switching signal is produced by the power factor controller and is based on a sinusoidal waveform that is independent of the waveform of an AC supply voltage for energizing an electric load.

Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits

Abstract: To achieve high performance and high integration density, the transistor dimensions are aggressively scaled down while lower power dissipation is achieved by scaling down the supply voltage. However, power distribution has become a challenging issue due to the severe switching noise on the power distribution network. Estimation of the worst case switching noise is essential to ensure the proper functionality of the VLSI circuits. In this paper, we propose a probabilistic approach to determine the lower bound of the worst case switching noise on power supply lines. The proposed algorithm traces the worst case input patterns which will induce the steepest maximum switching current spike and therefore the maximum switching noise. The worst case input patterns are used in the HSPICE simulation to extract the exact switching current waveforms. The estimated maximum switching current spike matches well with the peak current obtained from the HSPICE simulation. The worst case switching noise due to the lumped inductance (including the packaging inductance) and the lumped resistance on the power supply grid is also extracted from the HSPICE simulation. The magnitude of the worst case switching noise for the benchmark circuits implemented with 0.25 /spl mu/m technology can be as high as 35% of the Vdd. The switching noise can be suppressed effectively with properly placed decoupling capacitors.

Multi-layer chip capacitor

Abstract: An integrated circuit thin film capacitor includes multiple layers of conductors separated by dielectric material. The conductive layers are connected to interconnect lands using conductive vias. The interconnect lands can be controlled collapse chip connection (C4) lands that allow the capacitor to be connected to a circuit board. In one embodiment, the capacitor is mounted on a circuit board in close proximity to a processor circuit. The multi layer capacitor of the present invention provides the ability to increase a capacitance value while lowering interconnect resistance and inductance.

Optimal charging of capacitors

Abstract: Charging a capacitor from a voltage source with internal resistor is one of the basic problems in circuit theory. In recent years, this simple problem has attracted some interest in the area of low-power digital circuits. The efficiency, i.e., the energy stored in the capacitor versus the energy delivered by the source is one of the key measures. The common believe that the source has to deliver twice the capacitor energy holds true only for a linear circuit with step function as source voltage. In this paper we compute several optimal solutions with respect to time and efficiency. The case of nonlinear capacitors is discussed in some detail. The source voltage can depend on time in a rather involved manner. However, replacing the voltage source by a current source simplifies the problem significantly since the current has to be constant over time regardless of the characteristic of the capacitance. This result should have implications on the circuit technique employed for low power circuits. Furthermore, if leak conductances in parallel to the capacitor are taken into account, the achievable minimal energy dissipation is limited and, if ramps are used for charging, an optimal charging time different from infinity occurs.

High-speed sampler structures and methods

Abstract: High-speed sampler methods and structures are provided to enhance the correlation between an input signal Sin and a corresponding sampler output voltage Vout. An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor Cs is directly charged through the input buffer and the capacitor's bottom plate to a charge that corresponds to the input signal Sin. In the holding time periods, the disabled input buffer is isolated from the sampling capacitor Cs and a common-mode signal Scm is directly coupled to the capacitor's bottom plate to provide the output voltage Vout at the capacitor's top plate. Preferably, an output capacitor Co is coupled to the sampling capacitor Cs and charge from the sampling capacitor Cs is transferred to the output capacitor Co.

Method and apparatus for virtual current sensing in DC-DC switched mode power supplies

Abstract: An apparatus and method for virtual current sensing in a DC-DC switched mode power supply. In a fixed frequency implementation, when a switching phase begins, the phase node goes high when the high-side switching transistor is turned on. At this point, a first programmable current source begins charging a current sensing capacitor and the voltage across the capacitor simulates the rising slope of the voltage across a conventional current sensing resistor. Simultaneously, a ramp capacitor beginning at a reference voltage is charged by a second programmable current source. When the sum of the voltages across the two capacitors exceeds an error voltage, the phase node goes low when the drive signal to the transistor is turned off. At this point, a third programmable current source begins discharging the current sensing capacitor and the voltage across the capacitor simulates the falling slope of the current across the conventional resistor.

System and method for one-time programmed memory through direct-tunneling oxide breakdown

Abstract: A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

Chip decoupling capacitor

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V CC power bus and the other node directly V SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 μF.

Pattern forming method

Abstract: After a layout for a semiconductor device including power and ground lines has been defined, patterns for bypass capacitors, which will be located under the power lines, are created. In this case, a pattern for a semiconductor device, where a bypass capacitor array is inlaid and substrate contacts are located under ground lines, is defined based on design rules input. Next, power lines are extracted and resized. Thereafter, logical operations are performed to place the bypass capacitors and the bypass capacitors are resized. Subsequently, logical operations are performed to define interconnecting diffused layers and the diffused layers are resized. Since the patterns for the power lines have already been defined before the patterns for the bypass capacitors are created, the patterns for the bypass capacitors to be placed under the power lines can be defined automatically. Thus, a pattern for a miniaturized semiconductor device with reduced power supply noise can be created automatically.

Method and apparatus for eliminating displacement current from current measurements in a plasma processing system

Abstract: In a plasma processing system, displacement current is removed from a current measurement by providing a secondary capacitor connected in parallel with a primary capacitor defined by an anode and a cathode spaced from one another within the plasma doping chamber. The secondary capacitor is chosen or adjusted to have a same or nearly the same capacitance as the primary capacitor. When a voltage pulse is applied to both the primary and secondary capacitors, the respective currents through the capacitors are measured. In order to remove the effects of the displacement current that is present at the leading and falling edges of the voltage pulse, and in order to measure the ion current within the doping chamber, the secondary current through the secondary capacitor is subtracted from the primary current through the primary capacitor.

Electric double layer capacitor apparatus

Abstract: An electric double layer capacitor with a control circuit component. When the electric double layer capacitor is provided in plural and these capacitors are serially connected for charging thereof through a source of DC power, the control circuit component balances charge Voltage of each electric double layer capacitor. The control circuit component is mounted to a control circuit board. The control circuit board has a diameter smaller than that of a sheath can of the electric double layer capacitor and is fixedly secured to a cover such that it does not project upwardly beyond an upper end of a pole projection, serving as a positive electrode, of the electric double layer capacitor.

Sub-package bypass capacitor mounting for an array packaged integrated circuit

Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node. These vias preferably are spaced-apart a distance ΔX corresponding to the distance between first and second connections on the bypass capacitor although sub-mm offsets in a via at connections may be used to accommodate differing connection pitches. The bypass capacitor connections are coupled to the lower surfaces of the first and second vias, at the lower surface of the LGA package. When the package is inserted into a socket, the bypass capacitor extends into at least some of the otherwise unused recess in the socket. Multiple bypass capacitors are accommodated by forming additional spaced-apart vias that may be electrically parallel-coupled.

On-chip decoupling capacitor and method of making same

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. In one embodiment of the present invention, a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling.

A methodology for the placement and optimization of decoupling capacitors for gigahertz systems [CMOS VLSI]

Abstract: This paper discusses a method for computing the effect of decoupling capacitors on the power delivery system for gigahertz packages and boards. A fast and accurate computational method is presented that can be used to estimate the amount of decoupling required, the type of capacitor to be used and its location (on-chip, package or board).

Programmable gain ADC

Abstract: A programmable gain circuit for analog-to-digital converter. A switched capacitor network capacitively couples an analog reference from a DAC to a comparator so that the sampled amplitude of the input analog signal can be compared with said analog reference. The ratio of the capacitance of the sampling capacitor to that of the switched capacitor network establishes an effective gain to the analog signal being converted.

Methods for forming decoupling capacitors

Abstract: A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings. During this step the first type dopant is disposed into the gate. The substrate having the first type dopant comprises one terminal of the capacitor and the gate comprises another terminal of the capacitor.

Power-factor correction circuit of electronic ballast for fluorescent lamps

Abstract: A power-factor correction circuit of an electronic ballast for fluorescent lamps which includes an input full-wave rectification circuit for full-wave rectifying an AC input voltage from an AC input power source, a DC-link capacitor for supplying a DC-link voltage in response to an output voltage from the rectification circuit and a resonant inverter connected in parallel to the DC-link capacitor. The power-factor correction circuit comprises a charge pumping circuit disposed between the AC input power source and the rectification circuit, a valley-fill DC voltage supply circuit disposed between the rectification circuit and the DC-link capacitor, and a high-frequency full-wave rectification circuit disposed between the DC voltage supply circuit and the DC-link capacitor and connected to a secondary winding of a power transformer in the resonant inverter. The high-frequency full-wave rectification circuit includes a first pole connected to the secondary winding of the power transformer and a second pole connected to a common connection point of a plurality of stabilizing capacitors connected in series respectively to the fluorescent lamps. Therefore, a power factor of the ballast is improved and power supply is automatically controlled according to the number of fluorescent lamps being turned on.

Drive circuit for liquid-crystal displays and liquid-crystal display including drive circuits

Abstract: Disclosed is a liquid-crystal drive circuit having a simple configuration and being not susceptible to the characteristic of a device. The liquid-crystal drive circuit includes an auxiliary capacitor, applies a first voltage to a driving buffer, temporarily accumulates an output voltage of the driving buffer in the auxiliary capacitor, applies a voltage produced by subtracting the potential at the auxiliary capacitor from a second voltage to the driving buffer, and applies an output of the driving buffer onto a data bus.

Alternator power converter

Abstract: The present invention provides an alternator having a small size and a high reliability wherein, the alternator is equipped with a switching power module 1 having a resin case 13 housing switching elements 2 and a driving circuit section 5, a smoothing capacitor 7 for smoothing a direct current output supplied to the switching elements 2, a control circuit section 6 for outputting a control signal to the driving circuit section 5 and a cooling member 24; a ceramic capacitor is used as the smoothing capacitor; a smoothing capacitor board 25 for mounting the smoothing capacitor 7 is disposed between an insulating board mounting with the switching elements 2 and a driving circuit board 18 mounting with the driving circuit section 5; and the smoothing capacitor board 25 functions also as an electromagnetic shielding plate for protecting the driving circuit section 5 against the switching noise of the switching elements.

Energy and weight efficient flow-through capacitor, system and method

Abstract: An energy efficient flow-through capacitor, particularly for the concentration and/or separation of seawater. The flow-through capacitor is successively charged and discharged prior to the cell voltage exceeding 1.5 volts.

Tunable on-chip capacity

Abstract: The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors. By tuning the total capacity (CSD) of the decoupling capacitors a resonance condition of the resonance loop (40) is met under which a minimum of switching power noise and a minimum switching power consumption is achieved.

Clock duty cycle correction circuit

Abstract: A duty cycle correcting circuit is described having a first capacitor connected between a first node and a reference node and a second capacitor connected between a second node and the reference node. When the duty cycle of the output clock signal is greater than 50% the voltage across the second capacitor decreases thereby increasing the charging rate of the first capacitor, decreasing the discharging rate of the first capacitor, and restoring the output duty cycle to 50%. When the duty cycle of the output clock signal is less than 50% the voltage across the second capacitor increases thereby decreasing the charging rate of the first capacitor, increasing the discharging rate of the first capacitor, any restoring output duty cycle to 50%.

Switch capacitor circuit and applications thereof

Abstract: An improved switch capacitor circuit includes a capacitor, a 1st voltage reference module, a 2 nd voltage reference module, and a plurality of switching elements. The capacitor is operably coupled via the plurality of switching elements to sample an input signal during a 1 st interval of a sampling period and during a 2 nd interval of the sampling period to provide a representation of the input signal. The 2 nd reference module produces a 2 nd reference voltage that is representative of the common mode of the supply (e.g. V DD and V SS ). The 1 st voltage reference module produces a 1 st reference voltage that is representative of the common mode of the analog input signal. As such, the capacitor is charged during the 1 st interval based on the 1 st reference voltage and discharged during the 2 nd interval based on the 2 nd reference voltage.

Inrush current limiting circuit, power source device and power conversion device

Abstract: The present invention relates to an inrush current limiting circuit, a power source device and a power conversion device. It is an object of the present invention to limit an inrush current with high reliability and durability while reducing overall weight and volume of the device even under a high rated power. In order to achieve the object, a switch (11) a capacitor (12) and a switching element (30) are connected in series to one another, and the serial circuit formed thereof is connected to the main power source (10). An invester 13 is connected to the capacitor (12). A serial circuit formed of a capacitor (32) and a resistor (33) is connected between a collector and a gate of the switching element (30). A drive circuit (20) drives the switching element (30) to turn ON when the switch (11) turns ON.

Design and performance evaluation of microprocessor packaging capacitors using integrated capacitor-via-plane model

Abstract: As clock speeds increase into the gigahertz regime and rise times decrease into the picosecond regime, the interaction between capacitors and power/ground planes of a package, interposer, or board on which they are mounted becomes vitally important to the performance of a power delivery system. To include the interaction, this paper provides an integrated model for a discrete capacitor mounted on pads over vias connected to power/ground planes with degassing holes. The mutual inductance between capacitor pads, vias, and power/ground planes are completely modeled. Through optimized via and capacitor pads placement designs, our modeling results show that the mutual inductance drastically changes the total loop inductance as compared to the self-inductance of the capacitor. To validate the integrated modeling method, a test package is built. A measurement technique is introduced to evaluate the total loop inductance of the test package with various capacitor form factors and types. The predicted results match well with the measured data. This paper discusses further the usage of the three-dimensional (3-D) integrated model for actual implementation of decoupling capacitors on packages in order to ensure the effectiveness of the capacitors. The first decoupling capacitor placement design on package that we will discuss is the Plastic Pin Grid Array (PPGA) package for Intel's CPU. Through the three-dimensional (3-D) integrated modeling, the inductance value of the power delivery system with and without capacitors are extracted. It was found that due to the pin-out constraint of CPU PPGA products, as well as unfavorable PPGA package design rules, decoupling capacitors placed in PPGA packages are not effective due to high loop inductance. The second package that we will discuss is the Flip Chip Pin Grid Array (FC-PGA) package, which is for Intel's future CPU packaging. It is found that the decoupling capacitor placement on the FC-PGA highly improves the performance of the power delivery system. For the same amount of cost, the total loop inductance for FCPGA package decoupling capacitors is found to be 1/9th the total loop inductance for the PPGA package.

Extended adaptive voltage positioning (EAVP) [power delivery network design]

Abstract: The aim of this paper is to present a new robust approach, named extended adaptive voltage positioning (EAVP), to the design and analysis of a low impedance power delivery network. EAVP utilizes and extends on the theory of adaptive voltage positioning (AVP) that is commonly used in voltage regulator module (VRM) design and operation. Using EAVP, the authors demonstrate how uncertainties in design guardband noise budget can be removed, resulting in significant performance bin-split improvement and cost reduction. Design optimization of decoupling capacitors is illustrated using EAVP by using both time and frequency domain analysis.