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Showing papers on "Decoupling capacitor published in 2008"


Patent
04 Sep 2008
TL;DR: In this paper, a mechanism for in situ verification of capacitive power support is provided, where a memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted.
Abstract: A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested.

170 citations


Journal ArticleDOI
TL;DR: The optimal controller can reduce the THD of the AC currents or reduce the switching frequency at the same THD, being a suitable controller for power quality in medium-voltage applications.
Abstract: This paper presents the optimal control of the AC currents, the DC voltage regulation, and the DC capacitor voltage balancing in a three-level three-phase neutral point clamped multilevel converter for use in power quality applications as an active power filter. The AC output currents and the DC capacitor voltages are sampled and predicted for the next sampling time using linearized models and considering all the 27 output voltage vectors. A suitable quadratic weighed cost function is used to choose the voltage vector that minimizes the AC current tracking errors, the DC voltage steady-state error, and the input DC capacitor voltage unbalancing. The obtained experimental results show that the output AC currents track their references showing small ripple, a total harmonic distortion (THD) of less than 1%, harmonic contents that are 46 dB below the fundamental, and almost no steady-state error (0.3%). The capacitor voltages are balanced within 0.05%, and the balancing is assured even when redundant vectors are not chosen. Near-perfect capacitor DC voltage balancing is obtained while reducing current harmonic distortion. Some experimental evidence of robustness concerning a parameter variation was also found, with the optimum controller withstanding parameter deviations from +100% to -50%. Compared to a robust sliding mode controller, the optimal controller can reduce the THD of the AC currents or reduce the switching frequency at the same THD, being a suitable controller for power quality in medium-voltage applications.

165 citations


Journal ArticleDOI
TL;DR: A new method to detect the rise of equivalent series resistor in order to realize the online failure prediction of the electrolytic capacitor for LC filter of switching-mode power converter is proposed.
Abstract: The objective of this paper is to propose a new method to detect the rise of equivalent series resistor in order to realize the online failure prediction of the electrolytic capacitor for LC filter of switching-mode power converter. Characteristics of electrolytic capacitors are introduced in this paper. Different experimental measurements are conducted and shown to illustrate the properties of electrolytic capacitors. The proposed online failure prediction method has the merits of low cost and circuit simplicity. It can be integrated within the package of the electrolytic capacitor to improve its reliability. Hardware experimental results are shown to verify the performance of the proposed method.

123 citations


Journal ArticleDOI
TL;DR: In this article, the average energy effect of each vector on capacitor voltage and the necessary optimal vector state sequence in each modulation cycle were considered to balance the capacitor voltages, which minimizes the voltage rating overheads of the hardware and attenuates the negative effects associated with dc-link voltage oscillations.
Abstract: A requirement of the three-level neutral-point-clamped voltage source inverter, with or without a separately supporting dc link, is to maintain the balance of the two dc-link capacitor voltages. In this paper, balancing of the capacitor voltages for these two dc-link voltage source possibilities is analyzed and an algorithm is proposed to independently balance the capacitor voltages. The algorithm considers the average energy effect of each vector on capacitor voltage and the necessary optimal vector state sequence in each modulation cycle. The algorithm minimizes the voltage rating overheads of the hardware, reduces the voltage ripple, and attenuates the negative effects associated with dc-link voltage oscillations.

105 citations


Proceedings ArticleDOI
01 Nov 2008
TL;DR: In this paper, an LED driver requiring no electrolytic capacitor in the whole power conversion process is presented, which consists of two power conversion stages, one buck converter operating in discontinuous capacitor voltage mode, so that the input current is continuous, and the second stage is a current-fed inverter, in which the semiconductor switches are operated at constant switching frequency and constant duty cycle.
Abstract: An LED driver requiring no electrolytic capacitor in the whole power conversion process is presented It consists of two power conversion stages The first stage is a buck converter operating in discontinuous capacitor voltage mode, so that the input current is continuous It is used to deliver a regulated current for the second stage The second stage is a current-fed inverter, in which the semiconductor switches are operated at constant switching frequency and constant duty cycle of 05 The power supplying to the LED string is regulated by controlling the duty cycle of the main switch in the front-stage buck converter The two stages are interconnected by an LC filter, which is designed to attenuate harmonics at double of the line frequency Instead of using an electrolytic capacitor for the filter, a polyester capacitor of better lifetime expectancy is used An 18 W experimental prototype has been built and tested

104 citations


Journal ArticleDOI
TL;DR: A design methodology for placing on-chip decoupling capacitors is presented and a maximum effective radius is shown to exist for each on- chip decoupled capacitor.
Abstract: Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.

98 citations


Patent
20 Feb 2008
TL;DR: In this paper, a capacitive fingerprint sensor consisting of a fingerprint, a reference capacitor, a first transistor, a second transistor, and a comparator is configured to precharge the fingerprint and reference capacitors.
Abstract: A capacitive fingerprint sensor comprises a fingerprint capacitor, a reference capacitor, a first transistor, a second transistor, a comparator and a multiplexer. The fingerprint capacitor has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR, wherein CFV is smaller than CFR. One end of the reference capacitor CS is connected to the fingerprint capacitor, and the other end is connected to a trigger signal, wherein the trigger signal is initiated only during a precharge phase. The first transistor is configured to control the fingerprint capacitor during a scan line period. The second transistor is configured to precharge the fingerprint and reference capacitors. One end of the comparator is connected to the second transistor. The multiplexer is connected to another input end of the comparator for providing a first voltage VA and a threshold voltage Vth.

79 citations


Journal ArticleDOI
TL;DR: In this article, a single-ended and two-ended bidirectional capacitor multipliers for providing on-chip compensation, soft-start, and fast transient mechanisms are proposed.
Abstract: Single-ended and two-ended bidirectional capacitor multipliers for providing on-chip compensation, soft-start, and fast transient mechanisms are proposed in this paper. The bidirectional current mode capacitor multiplier technique can effectively move the crossover frequency toward to the origin in the start-up period for a smoothly rising of the output voltage. Besides, the small time constant is set by the fast transient control circuit in order to get a higher crossover frequency. Thus, the output voltage can be regulated to its stable value as fast as it can when large load current changes. A test chip fabricated by the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.35-m process verifies the correctness of the bidirectional current mode capacitor multiplier technique. Experimental results demonstrate the transient speed by our proposed technique is faster than that by conventional control by about 2 times, and there is only about 76% dropout voltage of the conventional design with off-chip compensation. The proposed circuits consume more quiescent current about 10 in single-ended capacitor multiplier and 20 in two-ended capacitor multiplier. With the proposed bidirectional current mode capacitor multiplier technique, the performance of dc-dc converters is improved significantly and the external pins and footprint area are minimized.

72 citations


Patent
23 Jul 2008
TL;DR: In this article, a voltage converter including a buck converter and a capacitive voltage divider is described. But the converter is not a voltage amplifier, it is a switch circuit, an inductor and a controller, and the inductor controls the duty cycle of the PWM signal to regulate the second output voltage.
Abstract: A voltage converter including a buck converter and a capacitive voltage divider. The converter includes four capacitors, a switch circuit, an inductor and a controller. A first capacitor is coupled between a reference node and a first output node which develops a first output voltage. A second capacitor is coupled between an input node and either the reference node or the first output node. The switch circuit couples a third capacitor between the reference and first output nodes in a first state of a PWM signal, and couples the third capacitor between the first output and input nodes in a second PWM signal state. The inductor is coupled to the third capacitor and provides a second output node coupled to the fourth capacitor providing a second output voltage. The controller controls the duty cycle of the PWM signal to regulate the second output voltage to a predetermined level.

64 citations


Patent
05 Aug 2008
TL;DR: In this paper, a multiple output DC-to-DC voltage converter using a new time-multiplexed-capacitor converter algorithm and related circuit topologies is described.
Abstract: A multiple output DC-to-DC voltage converter using a new time-multiplexed-capacitor converter algorithm and related circuit topologies is herein disclosed. One embodiment of this invention includes a flying capacitor, a first output node, a second output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the positive electrode of the flying capacitor is connected to an input voltage and the negative electrode of the flying capacitor is connected to ground; 2) a second mode where the negative electrode of the flying capacitor is connected to the input voltage and the positive electrode of the flying capacitor is connected to the first output node; and 3) a third mode where the positive electrode of the flying capacitor is connected to ground and the negative electrode of the flying capacitor is connected to the second output node.

64 citations


Patent
15 Feb 2008
TL;DR: In this article, a circuit and method for capacitor effective series resistance measurement is presented, which includes amplifying the capacitor voltage with an AC coupled amplifier, yielding a first amplified signal.
Abstract: A circuit and method for capacitor effective series resistance measurement. One embodiment provides a method for measuring the effective series resistance of a capacitor having a capacitor voltage. The method includes amplifying the capacitor voltage with an AC coupled amplifier yielding a first amplified signal. The capacitor is discharged with a constant current for a measurement time thus causing a voltage swing of the capacitor voltage due to a voltage drop across the effective series resistance. The capacitor voltage is amplified with the AC coupled amplifier yielding a second amplified signal being dependent on the voltage swing; calculating the effective series resistance from the first and the second amplified signal.

Patent
19 Mar 2008
TL;DR: In this paper, correlated double sampling is used to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage represented the offset alone.
Abstract: A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier.

Journal ArticleDOI
TL;DR: In this article, an energy capacitor system (ECS), which combines power electronic devices and electric double-layer capacitor, can significantly decrease voltage and power fluctuations of grid-connected fixed-speed wind generator.
Abstract: In this paper, it is reported that energy capacitor system (ECS), which combines power electronic devices and electric double-layer capacitor, can significantly decrease voltage and power fluctuations of grid-connected fixed-speed wind generator. The proper selection of wind farm output power reference is still a problem for smoothing the wind farm output power. This paper proposes exponential moving average to generate the reference output power of a grid-connected wind farm. The objective of the control system is to follow the line power reference by absorbing or providing real power to or from the ECS. Moreover, the necessary reactive power can also be supplied to keep the wind farm terminal voltage at the desired reference level. Real wind speed data were used in the simulation analyses, which validate the effectiveness of the proposed control strategy. Simulation results clearly show that our proposed ECS can be suitable for wind power application. Copyright © 2007 John Wiley & Sons, Ltd.

Journal ArticleDOI
TL;DR: In this article, the authors presented an analysis of the dynamic operation of unified power flow controller without DC link capacitance, where the capacitor in the DC link is replaced by an AC filter on the line side with a very small value to reduce higher order harmonics.

Patent
Boris Likhterov1
19 Jun 2008
TL;DR: In this article, a charge pump with a MOS-type capacitor is presented, where the MOS type capacitor is operated in an inversion region in which capacitance varies as a function of the frequency of the applied signal.
Abstract: A charge pump with a MOS-type capacitor, where the MOS-type capacitor is operated in an inversion region in which capacitance varies as a function of the frequency of the applied signal. The charge pump is switched to transfer charge from an input node to the capacitor and from the capacitor to an output node. During a transition interval, a relatively high frequency switching signal is used to lower the capacitance and increase efficiency. During a settling interval, a relatively low frequency switching signal is used, in which case the capacitance is higher, but similar to a level which would be seen if the capacitor was operated in an accumulation region. MOS capacitor dimensions and switching intervals are mutually optimized to provide high efficiency and required throughput. The charge pump may be configured as a voltage multiplier, divider, inverter or follower, for instance.

Proceedings ArticleDOI
15 Jun 2008
TL;DR: In this paper, the authors describe the measurement results of an integrated inductive DC-DC down converter, where the active electronics (power stage and driver circuitry) has been implemented in 0.18mum CMOS technology and the passive components (output LC filter and decoupling capacitor) were implemented in a state-of-the-art proprietary passiveintegration process technology using high-density trench-MOS capacitors (80 nF/mm2 ) and an 8mum thick copper top metallization layer.
Abstract: With the increasing number of voltage conversions that have to be efficiently implemented in a mobile device, the PCB space occupied by switched-mode DC-DC converters with external passive components will become unacceptably high. Therefore, a clear need exists for small-form-factor high-efficiency DC-DC converters having the necessary passive components integrated within one package. This will enable the integration of a DC-DC converter with the load and consequently the system integration of power management. This paper describes the measurement results of an integrated inductive down converter, where the active electronics (power stage and driver circuitry) has been implemented in 0.18-mum CMOS technology and the passive components (output LC filter and decoupling capacitor) have been implemented in a state- of-the-art proprietary passive-integration process technology using high-density trench-MOS capacitors (80 nF/mm2 ) and an 8-mum thick copper top metallization layer. The active die of the converter has been flip-chipped on top of the passive die to reduce parasitic component values. This yields a System-in-Package (SiP) that achieves a step-down DC-DC conversion without any external components. Due to the limited inductance achievable with the used planar air coil in the acceptable area, the switching frequency of the DC-DC converter has been increased. At the same time, Zero-Voltage-Switching (ZVS) measures have been implemented to reduce the switching losses at this increased frequency. A maximum efficiency of 65% at 80 MHz has been achieved for an input voltage of 1.8 V, an output voltage of 1.1 V and an output current of 100 mA. After explaining the motivation behind integrated power management and the choice for an integrated inductive converter, this paper describes the main design aspects of the realized integrated inductive DC-DC down converter. Next, it presents some details of the used passive-integration process, the design of the passive die including the LC filter and the construction of the SiP. Finally, the measurement results of the converter are discussed and conclusions are drawn.

Journal ArticleDOI
TL;DR: In this paper, a voltage-controlled oscillator (VCO) with low phase noise and low power dissipation for IEEE 802.11b is proposed, where a negative resistance multiple-gated circuit with a bypass capacitor is adopted to improve phase noise.
Abstract: A voltage-controlled oscillator (VCO) with low phase noise and low power dissipation for IEEE 802.11b is proposed. A negative resistance multiple-gated circuit with a bypass capacitor is adopted to improve phase noise. The chip is implemented in 0.18-mum CMOS process under a supply voltage of 0.9 V and power consumption of 2.7 mW. Its measured results show that the VCO has a phase noise of -122.3 dBc/Hz at 1-MHz offset frequency from the carrier frequency, and the tuning frequency from 2.17 to 2.73 GHz can be obtained under the tuning voltage of -0.9 to 0.9 V. The theoretical analysis and design consideration are also conducted in detail to show the benefits of the proposed VCO.

Patent
08 Oct 2008
TL;DR: In this paper, a method and device for predicting defects of a capacitor, including determining the ripple voltage (Udc), the temperature (TP), and the current (Ic), determining the value of an equivalent series resistance (ESR) of the capacitor, and the capacitance value (C) was presented.
Abstract: A method and device for predicting defects of a capacitor, the method including determining the ripple voltage (Udc), the temperature (TP), and the current (Ic) of the capacitor, determining the value of an equivalent series resistance (ESR) of the capacitor, and the capacitance value (C) of the capacitor using a digital filter, determining information representative of the state of aging of the capacitor according to the temperature of the capacitor, and displaying that information and information representative of the value of the capacitance (C) and/or information representative of a cause associated with the state of aging according to the capacitance value. The device may include a converter and an uninterruptible power supply.

Proceedings ArticleDOI
Jinsong Zhu1, A. Pratt1
15 Jun 2008
TL;DR: In this article, a methodology to calculate the ripple current, both for single phase and for m interleaved phases of power factor correction (PFC) converters operating with constant load or a DC-DC converter load, is presented.
Abstract: In order to achieve high power density in power supplies, it is desirable to minimize the physical size of the energy storage capacitor. The capacitance is determined by the energy storage requirement for line outage ride-through and also the ripple current handling capability of the capacitor. In cases where ripple current considerations dominate, interleaving is well known as an effective method to reduce the capacitor ripple current. This paper presents a methodology to calculate the ripple current, both for single phase and for m interleaved phases of power factor correction (PFC) converters operating with constant load or a DC-DC converter load. Experimental results from a commercial power supply yielded a small error when compared to the calculations, showing that the proposed methodology has enough accuracy to be used as a design tool.

Patent
14 Feb 2008
TL;DR: In this article, a magnetic core for generating a magnetic field, a power supply and a capacitor bank that is charged by the power supply is used for pulsing the magnetic core and a processor that measures a charging response of the capacitor bank during charging.
Abstract: The inventive technique includes methods, devices and computer-readable media for monitoring a magnetic device One such device includes a magnetic core for generating a magnetic field, a power supply and a capacitor bank that is charged by the power supply and is for pulsing the magnetic core The device also includes a processor that measures a charging response of the capacitor bank during charging and determines whether the measured charging response is within a predetermined tolerance of a predetermined charging response

Patent
08 Dec 2008
TL;DR: In this article, a method of generating a voltage supply (Vout+, Vout−) from a single input supply (+V DD ), comprising connecting at least one flying capacitor (Cf) to at least two reservoir capacitors (CR 1, CR 2 ) and to the input supply in repeated cycles so as to generate a voltage on said reservoir capacitor, was presented.
Abstract: A method of generating a voltage supply (Vout+, Vout−) from a single input supply (+V DD ), comprising connecting at least one flying capacitor (Cf) to at least one reservoir capacitor (CR 1 , CR 2 ) and to the input supply in repeated cycles so as to generate a voltage on said reservoir capacitor, the cycles differing between at least two modes so that each mode generates a different voltage on said reservoir capacitor the method including changing from an existing one of said modes to enter a new one of said modes during operation, and operating in at least one transitional mode for a period prior to entering fully said new mode

Patent
27 Mar 2008
TL;DR: In this article, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step.
Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Proceedings ArticleDOI
15 Jun 2008
TL;DR: In this article, the authors proposed a simple current control method for a voltage source inverter without the use of a large electrolytic capacitor in the dc link in order to compensate the low order harmonics in the output currents.
Abstract: Voltage source inverter plays an important role in modern industry. Conventional voltage source inverter has a large electrolytic capacitor as energy store element in order to keep the dc link voltage constant. However, a large electrolytic capacitor increases the input current distortion. Replacing the large electrolytic capacitor by a small film capacitor the input current quality is improved but the output currents are distorted by low order harmonics. This paper proposes a simple current control method for a voltage source inverter without the use of a large electrolytic capacitor in the dc link in order to compensate the low order harmonics in the output currents. The proposed current control scheme employs just one PI regulator and since that the space vector modulation is used in this control the switching frequency of the converter is kept constant.

Patent
Eric R. Fossum1
24 Sep 2008
TL;DR: In this article, a cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range, where charges accumulated in a first capacitor spill over into a second capacitor when a charge storage capacity of the first capacitor is exceeded.
Abstract: A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a second capacitor when a charge storage capacity of the first capacitor is exceeded. A third capacitor may also be provided such that charges accumulated by said second capacitor spill over into the third capacitor when the charge storage capacity of the second capacitor is exceeded.

Patent
19 Jun 2008
TL;DR: In this article, a change in the capacitance value of a sensor capacitor (CX) is detected by coupling it to a voltage supply (40), wherein said voltage supply is disconnected from a tank capacitor (c2) during said charging, transferring charge from a sensor to a tank during said charge transfer, and monitoring the voltage (VX) of the tank capacitor.
Abstract: Proximity of a person (BOD1) causes a change in the capacitance value of a sensor capacitor (CX) having a pair of capacitive plates (10a, 10b). Said change is detected by: - charging said sensor capacitor (CX) by coupling it to a voltage supply (40), wherein said voltage supply (40) is disconnected from a tank capacitor (C2) during said charging, - transferring charge from said sensor capacitor (CX) to a tank capacitor (C2), wherein said voltage supply (40) is disconnected from said tank capacitor (C2) during said charge transfer, - repeating said charging and charge transfer several times, - monitoring the voltage (VX) of said tank capacitor (C2), and - determining at least one value which depends on the rate of change of the voltage (VX) of said tank capacitor (C2). The capacitance of the capacitive sensor is typically low, typically in the order of 100 pF to 1 nF. The capacitance of the tank capacitor (C2) may be several orders of magnitude higher than the capacitance of the sensor capacitor (CX). The large tank capacitor (C2) acts as a part of a low-pass filter which effectively filters out signal noise.

Patent
Manabu Oyama1, Daisuke Uchimoto1
13 Nov 2008
TL;DR: In this paper, a charge pump circuit includes a first switch to a fourth switch, a flying capacitor, and an output capacitor, which are turned on and off on the basis of a pulse signal.
Abstract: A charge pump circuit includes a first switch to a fourth switch, a flying capacitor, and an output capacitor. A driver turns on the first switch and the fourth switch during a predetermined precharge period from the start of activation of the charge pump circuit to charge the output capacitor. Thereafter, on the basis of a pulse signal, the driver alternately turns on and off a first pair and a second pair.

Patent
08 Dec 2008
TL;DR: In this article, a top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed, which includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor die with the substrate, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members.
Abstract: A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.

Proceedings ArticleDOI
16 May 2008
TL;DR: In this article, a system in package (SiP) on which an input capacitor is mounted has been developed for voltage regulators, which offers the world's lowest power dissipation of 3.8 W at 1 MHz.
Abstract: A system in package (SiP) on which an input capacitor is mounted has been developed for voltage regulators. The SiP offers the world's lowest power dissipation of 3.8 W at 1 MHz. Its parasitic inductance is 44% lower than SiPs with the input capacitor mounted on the PCB, due to a small loop from the input capacitor to the MOSFETs, which reduces power dissipation by 25% at the same peak voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the MOSFET to the input capacitor. The lead frames and MOSFETs are connected with Cu leads, which reduce the spreading resistance of the MOSFET electrodes.

Patent
30 Jun 2008
TL;DR: In this paper, a two-stage power delivery network comprising both a switched capacitor stage and a buck regulator stage is proposed for power delivery to a microprocessor or other packaged integrated circuit (IC).
Abstract: Switched capacitor networks for power delivery to packaged integrated circuits. In certain embodiments, the switched capacitor network is employed in place of at least one stage of a cascaded buck converter for power delivery. In accordance with particular embodiments of the present invention, a two-stage power delivery network comprising both switched capacitor stage and a buck regulator stage deliver power to a microprocessor or other packaged integrated circuit (IC). In further embodiments, a switched capacitor stage is implemented with a series switch module comprising low voltage MOS transistors that is then integrated onto a package of at least one IC to be powered. In certain embodiments, a switched capacitor stage is implemented with capacitors formed on a motherboard, embedded into an IC package or integrated into a series switch module.

Patent
Shohtaroh Sohma1
20 Nov 2008
TL;DR: In this paper, a step-down switching regulator is proposed, where a switching element is a high-voltage NMOS transistor, turned on and off based on a control signal generated by a controller and charges an inductor with an input voltage input to an input terminal.
Abstract: In a step-down switching regulator, a switching element is a high-voltage NMOS transistor, turned on and off based on a control signal generated by a controller, and charges an inductor with an input voltage input to an input terminal. A first drive circuit is a low-voltage MOS transistor and turns on and off the switching element based on the control signal. A voltage generator generates a predetermined first power supply voltage not greater than a withstand voltage of the low-voltage MOS transistor. A capacitor is connected in parallel with the first drive circuit and stores charge from the voltage generator to supply power to the first drive circuit. One end of the capacitor is connected to a junction node between the switching element and the inductor, and the other end of the capacitor is supplied with the first power supply voltage generated by the voltage generator.