Showing papers on "Decoupling capacitor published in 2010"

Power transmission method of high-power wireless induction power supply system

Abstract: A power transmission method used in a high-power wireless induction power supply system consisting of a power-supplying module and a power-receiving module is disclosed. The power-supplying module regulates its output energy by means of frequency modulation and driving power adjustment, enabling the energy to be received by the power-receiving module and transmitted through a power-receiving coil array and a primary resonant capacitor and a secondary resonant capacitor of power-receiving resonance circuit, a synchronizing rectifier, a low-power voltage stabilizer, a high-frequency filter capacitor, a first power switch, a low-frequency filter capacitor and a second power switch of a filter circuit for output to an external apparatus.

Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation

Abstract: Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.

DC Capacitor Voltage Equalization in Neutral Clamped Inverters for DSTATCOM Application

Abstract: Multilevel neutral point clamped (NPC) inverter systems are increasingly used in load compensation applications. However, the most significant problem associated with these compensators is the capacitor voltage imbalances and drift due to dc components in the zero sequence current, resulting in degradation of tracking performance of the voltage source inverter. This paper proposes a carrier-based pulsewidth modulation control for an inverter-chopper circuit in order to regulate the capacitor voltages to their reference values. To demonstrate the simplicity and effectiveness of the aforementioned control scheme, a three-phase four-wire three-level NPC compensator system is taken as an example. Detailed simulation has been carried out in PSCAD 4.2.1. Experiments are conducted to validate the proposed control scheme.

A single-phase grid-connected inverter with power decoupling function

Abstract: This paper presents a single-phase grid connected inverter with a power decoupling circuit. In the single-phase grid connected inverter, it is well known that a power pulsation with twice the grid frequency is contained in the input power. In a conventional inverter, electrolytic capacitors with large capacitance have been used in order to smooth the DC voltage. However, lifetime of those capacitors is shortened by the power pulsation with twice grid frequency. The authors have been studied a active power decoupling (APD) method that reduce the pulsating power on the input DC bus line, this enables to transfer the ripple energy appeared on the input DC capacitors into the energy in a small film capacitor on the additional circuit. Hence, extension of the lifetime of the inverter can be expected because the small film capacitor substitutes for the large electrolytic capacitors. Effectiveness of the proposed method is confirmed through simulation and experimental results.

Memory device, semiconductor device, and electronic device

Abstract: An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

Abstract: Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65nm CMOS process. The ADC has an input capacitance of 180fF and occupies an active area of 0.03mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.

Capacitive touch sensing using an internal capacitor of an analog-to-digital converter (adc) and a voltage reference

Abstract: An internal sampling capacitor of an analog-to-digital converter (ADC) in a digital device is charged to a reference voltage, then some of the voltage charge on the internal.sampling capacitor is transferred to an external unknown capacitor through a low resistance switch internal to the digital device. After the charge transfer has stabilized, the voltage charge remaining on the internal sampling capacitor is measured. The difference between the known reference voltage and the voltage remaining on the internal sampling capacitor is used to determine the capacitance value of the external capacitor. Alternatively, the external capacitor may be charged to a reference voltage then the external capacitor is coupled to the internal sampling capacitor, e.g., having no charge or a known charge on it, and the resulting voltage charge on the internal sampling capacitor is measured and used for determining the capacitance value of the external capacitor.

Discharge Circuit for Smoothing Capacitor of DC Power Supply

Abstract: A discharge circuit for a DC power supply smoothing capacitor that is used in a power conversion device that supplies DC power via a switch to the DC power supply smoothing capacitor and an inverter, includes; a resistor that discharges charge in the capacitor; a switch connected in series with the resistor, that either passes or intercepts discharge current flowing from the capacitor to the resistor; a measurement circuit that measures a terminal voltage of the capacitor; and a control circuit that controls continuity and discontinuity of the switch; wherein the control circuit, after having made the switch continuous and starting discharge of the capacitor by the resistor, if a terminal voltage of the capacitor as measured by the measurement circuit exceeds a voltage decrease characteristic set in advance, makes the switch discontinuous and stops discharge by the resistor.

A generalized capacitor voltage balancing scheme for flying capacitor multilevel converters

Abstract: Multilevel power electronic converters are the converter of choice in medium-voltage applications due to their reduced switch voltage stress, better harmonic performance, and lower switching losses. Although it has received little attention, the flying-capacitor multilevel converter has a distinct advantage in terms of its ease of capacitor voltage balancing. A number of techniques have been presented in the literature for capacitor voltage balancing, some relying on “self-balancing” properties. However, self balancing cannot guarantee balancing of capacitor voltages in practical applications. Other researchers present closed-loop control schemes which force voltage balancing of capacitors. In this paper, a new closed loop control scheme is proposed which regulates the capacitor voltages for a multilevel flying capacitor converter. The proposed scheme is based on the converter equations and involves implementing simple rules. In particular, multiple duty cycles are defined and modulated in direct response to the capacitor voltages. Through simulation, the method is shown to work on four, eight and nine-level flying capacitor inverters.

Capacitor voltage balancing using redundant states of space vector modulation for five-level diode clamped inverters

Abstract: A redundancy balancing technique for the five-level diode-clamped inverter is presented, which balances the four dc-link capacitor voltages at high modulation index and high power factor. The technique is based on dividing the vector space of the five-level inverter into six two-level vector spaces. Dwell times are calculated as for conventional two-level space vector modulation, and the switching sequence is determined depending on the four capacitor voltages, using a redundant state method. The double Fourier series is used to theoretically determine the resultant spectral components. The proposed technique maintains link capacitor balance for high modulation indices, including over modulation, irrespective of the power factor. The proposed algorithm is validated by simulation and practically.

Single-Phase to Single-Phase Full-Bridge Converter Operating With Reduced AC Power in the DC-Link Capacitor

Abstract: This paper presents a control technique based on input and output AC power synchronization to reduce the low frequency AC power and the DC-link voltage fluctuation of a single-phase full-bridge converter. The control technique is based on a technique in which the load voltage is synchronized with the input grid voltage for both constant (Mode I) and variable (Mode II) phase angle. Such approach allows for a reduction in the capacitor size. A capacitor bank design approach is also proposed. The technique has been achieved for the same input and output converter frequency. Simulated and experimental results are addressed.

Recent Developments in Fault Detection and Power Loss Estimation of Electrolytic Capacitors

Abstract: This paper proposes a comparative study of current-controlled hysteresis and pulsewidth modulation (PWM) techniques, and their influence upon power loss dissipation in a power-factor controller (PFC) output filtering capacitors. First, theoretical calculation of low-frequency and high-frequency components of the capacitor current is presented in the two cases, as well as the total harmonic distortion of the source current. Second, we prove that the methods already used to determine the capacitor power losses are not accurate because of the capacitor model chosen. In fact, a new electric equivalent scheme of electrolytic capacitors is determined using genetic algorithms. This model, characterized by frequency-independent parameters, redraws with accuracy the capacitor behavior for large frequency and temperature ranges. Thereby, the new capacitor model is integrated into the converter, and then, software simulation is carried out to determine the power losses for both control techniques. Due to this model, the equivalent series resistance (ESR) increase at high frequencies due to the skin effect is taken into account. Finally, for hysteresis and PWM controls, we suggest a method to determine the value of the series resistance and the remaining time to failure, based on the measurement of the output ripple voltage at steady-state and transient-state converter working.

Physics-Based Inductance Extraction for Via Arrays in Parallel Planes for Power Distribution Network Design

Abstract: A systematic approach for inductance extraction for via arrays between two parallel planes is presented. Both self and mutual inductance values are obtained based on a cavity model. The physics associated with the via inductances is analyzed, and a rigorous method is developed to derive an equivalent total inductance for multiple via arrays. Analytical equations for the equivalent total inductance are derived in closed forms for simple cases. The proposed method is corroborated with measurements, and application of the method for power distribution network designs is demonstrated.

Optimal Capacitor Placement in a Radial Distribution System using Harmony Search Algorithm

Abstract: Modern electric energy are generated from generating station and it deliver to the customer through transmission and distribution network. Most electrical equipment such as motors, lamps and heaters required constant voltage in order to operate. Transmission and distribution system are not required to carry active power but it must also carry magnetizing for inductive load at consumer side. It is essential that the generator at generating station produce active and reactive power. In order to supply and produce reactive power, shunt capacitor are widely used. There are several benefit of shunt capacitor installation in distribution system such as reactive power compensation, power factor correction, system capacity released , power support , reduction in loss and voltage improvement. In this study, the placement of shunt capacitor and optimal capacitor size will be carried out. The result are then compare with others technique in term of capacitor installation cost saving. In this study, loss reduction and voltage profile improvement are studied. It is shown that almost 14% of the losses contribute at distribution system. It also very important to determine the appropriate location of capacitor in order to reduce the system power loss and total capacitor cost. In this study, the main objective is to find the optimal capacitor placement using a new meta-heuristic approach, Harmony Search Algorithm in radial distribution system which is then to reduce power loss and improve the system voltage profile. Simple backward forward sweep power flow is used to determine the power flow in the system. The performance of proposed algorithm is test using 9 bus system and compare with other meta-heuristic approach, Particle Swarm Optimization.

A life prediction scheme for electrolytic capacitors in power converters without current sensor

Abstract: Predicting the expected life of switching power supply is essential since unexpected failure of the subsystem can produce enormous loss. Electrolytic capacitor is the weakest among various power components in a power converter. Monitoring the Equivalent Series Resistance (ESR) variation of the electrolytic capacitor, achieving by voltage and current ripple, can estimate the converter life. Currently, Hall Effect sensor or others are current sensing options but all of them add series impedance to the capacitor and deteriorate capacitor voltage waveform. A sensor-less current waveform prediction method is proposed. Popular current mode control with the switch current signal is used. Repetitive sampling on the switch current allows capacitors current waveforms prediction without any current sensor at capacitor nodes. Together with the voltage waveform acquired, the ESR value can be calculated.

A new circuit design and control to reduce input harmonic current for a three-phase ac machine drive system having a very small dc-link capacitor

Abstract: This paper presents a new circuit topology to meet the input harmonic current standard for an ac machine drive system which has a very small dc-link capacitor. The proposed circuit topology is based on a harmonic current injection method, and it keeps up size and cost competitiveness of an ac machine drive system having a very small dc-link capacitor. Also, this paper proposes an appropriate control algorithm and a stability analysis for the proposed circuit topology. Experimental results reveal the validity of the proposed circuit topology and its control method. Also, it is confirmed that the harmonic current standard can be satisfied with the proposed circuit and its control method.

Smart Electronic Switch for Low-Power Loads

Abstract: A two-wire smart load control device, such as an electronic switch, for controlling the power delivered from a power source to an electrical load comprises a relay for conducting a load current through the load and an in-line power supply coupled in series with the relay for generating a supply voltage across a capacitor when the relay is conductive. The power supply controls when the capacitor charges asynclironously with respect to the frequency of the source. The capacitor conducts the load current for at least a portion of a line cycle of the source when the relay is conductive. The load control device also comprises a bidirectional semiconductor switch, which is controlled to minimize the inrush current conducted through the relay. The bidirectional semiconductor switch is rendered conductive in response to an over-current condition in the capacitor of the power supply, and the relay is rendered non-conductive in response to an over-temperature condition in the power supply.

Capacitive sensor system with noise reduction

Abstract: A system for reducing noise when detecting the capacitance value of a capacitor in a touch display that operates in a potentially noisy environment. A capacitance sensor is provided for determining the size of the capacitor in the touch screen display and includes a charging circuit that charges the capacitor and a discharge circuit that resets the charge of the capacitor to substantially zero. A control circuit controls the capacitance sensor and the operation of the charge and discharge circuits in accordance with a predetermined charging/discharging algorithm to resolve the value of the capacitor and output such value in a sampling operation. The operation of the control circuit and the charging/discharging algorithm is subject to errors as a function of the noisy environment, which errors will be reflected in the output value. A noise reduction circuit is provided to modify the operation of the control circuit to reduce noise.

Effective use of film capacitors in single-phase PV-inverters by active power decoupling

Abstract: The lifetime and reliability of PV-inverters can be increased by replacing electrolytic capacitors by film-capacitors Film-capacitors have a lower capacitance per volume ratio; therefore a direct replacement leads to very large and expensive solutions, especially for single-phase applications This paper presents an active circuit which acts as an interface between the DC-link of a PV-inverter and an additional storage capacitor The voltage ripple in the storage capacitor can be increased compared to the DC-link capacitor, allowing a more efficient use of the stored energy and thus a massive reduction of the overall installed capacitance An especially promising application can be found in module-integrated PV-inverters, because here the most efficient and cheapest topologies suffer from big electrolytic capacitors which deteriorate the lifetime The paper focuses on different possible control schemes of the decoupling circuit Results from simulations are used for discussing the proposed control methods Also results from an experimental efficiency comparison between systems with electrolytic and film-capacitors are given Finally a lab-prototype of the decoupling-circuit is presented which will be used for further experiments

Simple Experimental Techniques to Characterize Capacitors in a Wide Range of Frequencies and Temperatures

Abstract: The aim of this paper is to present two very simple, cheap, and practical experimental techniques that are able to estimate the capacitor equivalent circuit for a wide range of frequencies and temperatures. The capacitor equivalent circuit considerably changes with temperature, aging, and frequency. Therefore, knowledge of their equivalent circuit at their operating conditions can lead to better design proposals. In addition, knowledge of the evolution of the equivalent series resistance (ESR) with temperature is essential for the development of reliable online fault diagnosis techniques. This issue is particularly important for aluminum electrolytic capacitors, since they are the preferred capacitor type in power electronics applications and simultaneously one of the most critical components in such applications. To implement the first technique, it is necessary to put the capacitor under test in series with a resistor and connect it to a sinusoidal voltage. The second technique requires a simple charge-discharge circuit. After acquiring both capacitors' current and voltage through an oscilloscope, which is connected to a PC with Matlab software, it is possible to compute both capacitor capacitance and resistance using the least mean square (LMS) algorithm. To simulate the variation of capacitor case temperature, a very simple prototype was used. Several experimental results were obtained to evaluate the accuracy and precision of the two experimental techniques.

Supply-regulated phase-locked loop (pll) and method of using

Abstract: A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times CUNIT, where N is the current value of a multiplication factor of a divide-by-N circuit and CUNIT is a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.

Insulation state detector

Abstract: An insulation state detector includes a capacitor, a measurement section measuring a charging voltage of the capacitor, a measuring circuit that connects the capacitor, which is insulated from a DC power source after being charged by the DC power source, between the measurement section and a ground potential portion, a detector detecting an insulation state of a voltage boosting circuit, and a reversed-polarity measuring circuit that connects the capacitor to the measurement section and the ground potential portion with reversed polarity when a potential corresponding to a division ratio of a positive-side ground fault resistor and a negative-side ground fault resistor on a secondary side of the voltage boosting circuit exceeds a positive potential of the DC power source and the capacitor is charged with reversed polarity by a secondary-side positive potential at the time of charging of the capacitor using the positive potential of the DC power source.

Multiple-stage charge pump with charge recycle circuit

Abstract: A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit, and the second pump capacitor, the second transfer circuit and the second driving circuit form a second stage circuit. The first and the second stage circuits operate 180 degree out of phase with each other. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in a first time interval, and transferring the charge at the second end of the second pump capacitor to the second end of the first pump capacitor in a second time interval.

Driving apparatus for a vehicle-mounted electric motor

Abstract: An inverter circuit for a motor outputs three-phase AC currents, which are outputted from common connection points to stator coils, based on output voltage of a DC power source and a power supply capacitor by a switching operation of transistors. An inverter control circuit determines that a system main relay is turned off, upon receiving a main relay-off signal from an electronic control unit. The inverter control circuit turns on the low-side transistors, while turning off the high-side transistors. A discharge current flows from the positive electrode to the negative electrode of the power supply capacitor through the stator coil and the low-side transistors, so that electric charge stored in the power supply capacitor is discharged.

Systematic Microwave Network Analysis for Multilayer Printed Circuit Boards With Vias and Decoupling Capacitors

Abstract: An efficient microwave network method is proposed for signal and power integrity analysis of a multilayer printed circuit board with multiple vias and decoupling capacitors. The multilayer parallel plate structure is described as a cascaded microwave network. The admittance matrix of a single plate pair with ports defined in via holes both on top and bottom plates is obtained through the intrinsic via circuit model and impedance matrix between two plates. A recursive algorithm is provided to obtain the combined admittance matrix of two layers of plate pair coupled through via holes on a common plate. Decoupling capacitors are naturally treated as impedance loads to the cascaded admittance network. Numerical simulations and measurements have been used to validate the method and good agreements have been observed. While the method is as accurate as full-wave numerical solvers, it achieves much higher efficiencies both in CPU time and memory requirements.

A 2.45-GHz low cost and efficient rectenna

Abstract: This paper reports a novel rectifying antenna (rectenna) based on modified bridge rectifier with four Schottky diodes. The 2.45-GHz microwave rectifier has been developed and optimized using a global simulation technique which associates electromagnetic and circuit approaches in order to accurately predict the rectifier performances. The presented device doesn't need neither input HF filter nor bypass capacitor. This makes the structure more compact and low cost. A 2.45GHz linearly polarized patch antenna has been designed and associated to the microwave rectifier to obtain the full rectenna. The rectifier achieves an RF-to-dc conversion efficiency of 61% at 10 mW input power. When the power density is 0.15 mW/cm², the full rectenna circuit shows an efficiency of 52% over an optimal resistive load of 1050Ω.

Predictive simulation of CDM events to study effects of package, substrate resistivity and placement of ESD protection circuits on reliability of integrated circuits

Abstract: Power domain crossing circuits, also known as internal I/O's, are susceptible to gate oxide damage during charged device model (CDM) events. Circuit-level simulations of internal I/O circuits along with elements representing the package, electro-static discharge (ESD) circuits and the substrate, elucidate the roles of the package, power clamp placement, back-to-back diode placement and the decoupling capacitors in determining the amount of stress at the internal I/O circuits. This paper presents an internal I/O model that can be used for CDM simulations. The effects of power and ground bus resistance, substrate resistivity, decoupling capacitance, local ESD clamp at the gate of the receiver and the presence of local back-to-back diodes are investigated. The paper further contains design recommendations for preventing CDM failures in the internal I/O circuits.

Externally fused and resistively loaded safety capacitor

Abstract: A capacitor with a combined with a resistor and/or fuse is described. This safe capacitor can rapidly discharge through the resistor when shorted. The presence of a fuse in series with the capacitor and results in a resistive failure when this opens during and overcurrent condition. Furthermore, the presence of a resistor in parallel to the capacitor allows the energy to be rapidly dissipated when a failure occurs.

Transformer with bypass capacitor

Abstract: An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors.