Showing papers on "Decoupling capacitor published in 2013"

A Review of Power Decoupling Techniques for Microinverters With Three Different Decoupling Capacitor Locations in PV Systems

Abstract: The reliability of the microinverter is a very important feature that will determine the reliability of the ac-module photovoltaic (PV) system. Recently, many topologies and techniques have been proposed to improve its reliability. This paper presents a thorough study for different power decoupling techniques in single-phase microinverters for grid-tie PV applications. These power decoupling techniques are categorized into three groups in terms of the decoupling capacitor locations: 1) PV-side decoupling; 2) dc-link decoupling; and 3) ac-side decoupling. Various techniques and topologies are presented, compared, and scrutinized in scope of the size of decoupling capacitor, efficiency, and control complexity. Also, a systematic performance comparison is presented for potential power decoupling topologies and techniques.

Active Power Decoupling for High-Power Single-Phase PWM Rectifiers

Abstract: Single-phase pulsewidth modulation rectifiers suffer from ripple power pulsating at twice the line frequency. The ripple power is usually filtered by a bulky capacitor bank or an LC branch, resulting in lower power density. The alternative way is active power decoupling, which uses an active circuit to direct the pulsating power into another energy-storage component. The main dc-link filter capacitor can, therefore, be reduced substantially. This paper proposed a new scheme of active power decoupling. The circuit consists of a third leg, an energy-storage capacitor and a smoothing inductor. The topology combined the advantages of high energy-storage efficiency and low requirement on control bandwidth. Both the pulsating power from the ac source and the reactive power of the smoothing inductors are taken into consideration when deriving the power decoupling scheme. The active power filter's (APF) capacitor voltage control system consists of inner loop pole-placement control and outer loop proportional-resonant control. To enhance the steady-state performance, the capacitor voltage reference is modified in a closed-loop manner. Simulation and experimental results show that the proposed APF scheme has good power decoupling performance and is more suited for high-power applications where switching frequency is limited.

A Single-Stage Microinverter Without Using Eletrolytic Capacitors

Abstract: This paper presents a new microinverter topology that is intended for single-phase grid-connected PV systems. The proposed microinverter topology is based on a flyback converter, where an extra switch is added to separate the decoupling capacitor from the PV Module, which allows for a high voltage and voltage ripples across its terminals. This results in reducing the power decoupling required capacitance. In this manner, long life-time low power density film capacitors can be used instead of life-time limited high power density electrolytic capacitors, resulting in remarkable increase of microinverter's lifespan. The main advantages of the proposed topology are summarized as: 1) eliminating the double-frequency power ripple using a small film capacitor; 2) using long lifetime film capacitors, which will improve the reliability of the inverter; and 3) requiring no additional circuitry to manage the transformer leakage energy. A 100-W microinverter prototype was built to verify the proposed topology. Experimental results show that the proposed topology and its control scheme can realize the power decoupling, while maintaining very good conversion efficiency numbers.

Reliability of Candidate Photovoltaic Module-Integrated-Inverter (PV-MII) Topologies—A Usage Model Approach

Abstract: This paper proposes a new methodology for calculating the mean time between failure (MTBF) of a photovoltaic module-integrated inverter (PV-MII). Based on a stress-factor reliability methodology, the proposed technique applies a usage model for the inverter to determine the statistical distribution of thermal and electrical stresses for the electrical components. The salient feature of the proposed methodology is taking into account the operating environment volatility of the module-integrated electronics to calculate the MTBF of the MII. This leads to more realistic assessment of reliability than if a single worst case or typical operating point was used. Measured data (module temperature and insolation level) are used to experimentally verify the efficacy of the methodology. The proposed methodology is used to examine the reliability of six different candidate inverter topologies for a PV-MII. This study shows the impact of each component on the inverter reliability, in particular, the power decoupling capacitors. The results confirm that the electrolytic capacitor is the most vulnerable component with the lowest MTBF, but more importantly provide a quantified assessment of realistic MTBF under expected operating conditions rather than a single worst case operating point, which may have a low probability of occurrence.

Optimization of Switching Losses and Capacitor Voltage Ripple Using Model Predictive Control of a Cascaded H-Bridge Multilevel StatCom

Abstract: This paper further develops a model predictive control (MPC) scheme which is able to exploit the large number of redundant switching states available in a multilevel H-bridge StatCom (H-StatCom). The new sections of the scheme provide optimized methods to tradeoff the harmonic performance with converter switching losses and capacitor voltage ripple. Varying the pulse placement within the modulation scheme and modifying the heuristic model of the voltage balancing characteristics allows the MPC scheme to achieve superior performance to that of the industry standard phase shifted carrier modulation technique. The effects of capacitor voltage ripple on the lifetime of the capacitors are also investigated. It is shown that the MPC scheme can reduce capacitor voltage ripple and increase capacitor lifetime. Simulation and experimental results are presented that confirm the correct operation of the control and modulation strategies.

Predictive sorting algorithm for modular multilevel converters minimizing the spread in the submodule capacitor voltages

Abstract: The modular multilevel converter is a suitable topology for bidirectional ac-dc conversion in high-voltage high-power applications. By connecting submodule circuits in series, a high-voltage waveform with excellent harmonic performance can be achieved with a very high efficiency and low switching frequency. The balancing of the capacitor voltages will, however, become increasingly difficult as the switching frequency is reduced. Although the capacitor voltages can be kept balanced over time even at the fundamental switching frequency, the spread and thus also the peak variation in the capacitor voltages will typically increase at lower switching frequencies. This paper presents a capacitor voltage balancing strategy which aims to combine a low switching frequency with a low capacitor voltage ripple. This is done by a predictive algorithm that calculates the amount of charge that must be stored in the submodule capacitors during the following fundamental frequency period. The converter is then controlled in such a way that the stored charge in the submodule capacitors is evenly distributed among all the submodules when the capacitor voltages reach their maximum values. In this way, it is possible to limit the peak voltage in the capacitor at switching frequencies as low as 2-3 times the fundamental frequency. The capacitor voltage balancing strategy is first validated by simulation results at 110 Hz switching frequency. It is observed that when the proposed method is used, the capacitor voltage ripple is 35% lower compared to the case when a conventional sorting algorithm is used. The capacitor voltage balancing strategy is also validated experimentally at 130 Hz switching frequency. The experimental results show that it is possible to combine the proposed method with previously presented circulating-current control methods.

Adaptive Voltage Control of the DC/DC Boost Stage in PV Converters With Small Input Capacitor

Abstract: In the case of photovoltaic (PV) systems, an adequate PV voltage regulation is fundamental in order to both maximize and limit the power. For this purpose, a large input capacitor has traditionally been used. However, when reducing that capacitor's size, the nonlinearities of the PV array make the performance of the voltage regulation become highly dependent on the operating point. This paper analyzes the nonlinear characteristics of the PV generator and clearly states their effect on the control of the dc/dc boost stage of commercial converters by means of a linearization around the operating point. Then, it proposes an adaptive control, which enables the use of a small input capacitor preserving at the same time the performance of the original system with a large capacitor. Experimental results are carried out for a commercial converter with a 40 μF input capacitor, and a 4 kW PV array. The results corroborate the theoretical analysis; they evidence the problems of the traditional control, and validate the proposed control with such a small capacitor.

Decoupling Capacitor Selection in DCM Flyback PV Microinverters Considering Harmonic Distortion

Abstract: Electrolytic capacitors as a decoupling reservoir restrict the lifetime of photovoltaic (PV) microinverters This has led to the development of several improved decoupling circuits that can reduce the capacitor value to allow the use of nonelectrolytic types In this paper, the minimum decoupling capacitor value for the proper operation of discontinuous conduction mode flyback PV microinverters is analyzed by taking into account the total harmonic distortion (THD) and PV power utilization ratio The results presented show that the decoupling capacitor value influences the THD more than PV power utilization A decoupling capacitor selection method for single-stage and two-stage flyback inverters is proposed Experimental results obtained on an 80-W test bench are presented

An 84.7% Efficiency 100-MHz Package Bondwire-Based Fully Integrated Buck Converter With Precise DCM Operation and Enhanced Light-Load Efficiency

Abstract: A 100-MHz PWM fully integrated buck converter utilizing standard package bondwire as power inductor with enhanced light-load efficiency which occupies 2.25 mm2 in 0.13-μm CMOS is presented. Standard package bondwire instead of on-chip spiral metal or special spiral bondwire is implemented as power inductor to minimize the cost and the conduction loss of an integrated inductor. The accuracy requirement of bondwire inductance is relaxed by an extra discontinuous-conduction-mode (DCM) calibration loop, which solves the precise DCM operation issue of fully integrated converters and eliminates the reverse current-related loss, thus enabling the use of standard package bondwire inductor with various packaging techniques. Optimizations of the power transistors, the input decoupling capacitor (CI), and the controller are also presented to achieve an efficient and robust high-frequency design. With all three major power losses, conduction loss, switching loss, and reverse current related loss, optimized or eliminated, the efficiency is significantly improved. An efficiency of 74.8% is maintained at 10 mA, and a peak efficiency of 84.7% is measured at nominal operating conditions with a voltage conversion of 1.2 to 0.9 V. Converters with various bondwire inductances from 3 to 8.5 nH are measured to verify the reliability and compatibility of different packaging techniques.

A 4.6W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS

Abstract: The future trends in microprocessor supply current requirements represent a bottleneck for next generation high-performance microprocessors since the number of supply pins will constitute an increasingly larger fraction of the total number of package pins available. This leaves few pins available for signaling. On-chip power conversion is a means to overcome this limitation by increasing the input voltage - thereby reducing the input current - and performing the final power conversion on the chip itself. This paper details the design and implementation of on-chip switched capacitor converters in deep submicron technologies. High capacitance density deep trench capacitors with a low parasitic bottom plate capacitor ratio available in the technology facilitate high power density and efficiency in on-chip switched capacitor converter implementations. The measured performance of a 2 : 1 voltage conversion ratio on-chip switched capacitor converter implemented in 32nm SOI CMOS technology with 1.8V input voltage results in a power density of 4.6W/mm2 at 86% efficiency when operated at a switching frequency of 100MHz.

A High-Efficiency Wide-Input-Voltage Range Switched Capacitor Point-of-Load DC–DC Converter

Abstract: The traditional inductor-based buck converter has been the default design for switched-mode voltage regulators for decades. Switched capacitor (SC) dc-dc converters, on the other hand, have traditionally been used in low-power ( 80% over a load range of 5 mA to 1 A) than surveyed competitive buck converters, while requiring less board area and less costly passive components. The topology and controller enable a wide input range of 7.5-13.5 V. Controls based on feedback and feedforward provide tight regulation under worst case line and load step conditions. This study shows that the SC converter can outperform the buck converter, and thus, the scope of SC converter application can and should be expanded.

A frequency-domain study on the effect of DC-link decoupling capacitors

Abstract: DC-link decoupling capacitors are generally placed near the power switches in the converter to minimize the parasitic ringing and voltage overshoot on the devices. In this paper, the influence of decoupling capacitors on the turn-off parasitic ringing of power MOSFETs is studied in the frequency domain based on a small-signal modeling approach. This new angle helps explain the effect of these capacitors in a simpler and more straightforward way compared to the traditional time-domain analysis, and provides a deeper insight into the problem. A rule of thumb about the selection of effective decoupling capacitance value can also be derived from this study.

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Abstract: 3-D integration presents a path to higher performance, greater density, increased functionality and heterogeneous technology implementation. However, 3-D integration introduces many challenges for power and thermal integrity due to large switching currents, longer power delivery paths, and increased parasitics compared to 2-D integration. In this work, we provide an in-depth study of power and thermal issues while incorporating the physical design characteristics unique to 3-D integration. We provide a qualitative perspective of the power and thermal dissipation issues in 3-D and study the impact of Through Silicon Vias (TSVs) size for their mitigation. We investigate and discuss the design implications of power and thermal issues in the presence of decoupling capacitors, TSV/on-die/package parasitics, various resonance effects and power gating. Our study is based on a ten-tier system utilizing existing 3-D technology specifications. Based on detailed power distribution and heat dissipation models, we present a comprehensive analysis of TSV tapering for alleviating power and thermal integrity issues in 3-D ICs.

A high efficiency resonant switched capacitor converter with continuous conversion ratio

Abstract: A resonant switched capacitor converter with high efficiency over a wide and continuous conversion ratio is introduced. The efficiency of the topology depends primarily on the conduction losses and is decoupled, to a large extent, from the voltage conversion ratio. This is an advantage over classical switched capacitor converters in which the efficiency is strongly related to the conversion ratio. The operation principle applies three zero current switching (ZCS) states to charge, discharge and balance the remaining charge of the flying capacitor. This results in a Gyrator-behaved voltage-dependent current source with a wide voltage conversion ratio (smaller as well as greater than unity) as well as bidirectional power flow capabilities. The analytical expressions for conversion ratio and expected efficiency are provided and validated by simulation and experiments. The experimental verification of the converter demonstrates peak efficiency of 96%, and above 90% efficiency over a wide range of voltage gains and loading conditions. In addition, the system was found to be highly efficient at the extreme cases of both light and heavy loads.

Reconfigurable switched capacitor power converter techniques

Abstract: An apparatus for converting a first voltage into a second voltage includes a reconfigurable switched capacitor power converter having a selectable conversion gain. converter includes a cascade multiplier switched capacitor network having capacitors, each of which electrically connects to a stack node and to a phase node. A controller causes the network to transition between first and second operation modes. In the first mode, at least one capacitor is isolated from a charge transfer path of the reconfigurable switched capacitor power converter. Consequently, in the first mode of operation, the power converter operates with a first gain. In the second mode, the power converter operates with a second conversion gain. Meanwhile, a third voltage across the at least one capacitor is free to assume any value.

Improved pulse-width modulation and capacitor voltage-balancing strategy for a scalable hybrid cascaded multilevel converter

Abstract: This study re-introduces a hybrid multilevel converter that is capable of operating independent of load power factor and modulation index plus is applicable to medium- to high-voltage application. These features are achieved by adopting a new modulation strategy that utilises third harmonic subtraction in order to: increase the modulation index linear range, have a smaller capacitor size and smaller footprint, have zero net power exchange between the cell capacitors, and the load is guaranteed for all operating conditions. This study establishes an optimal magnitude of third harmonic to be subtracted by the H-bridge cells to ensure proper converter operation. The validity of the presented modulation strategy and capacitor voltage balancing are confirmed by simulation and experimentation on a scaled-down model and prototype. The scalability of the hybrid multilevel converters to high-voltage application is demonstrated using simulation, including start-up and shut down without the need for auxiliary circuitry.

Fully Integrated Capacitive DC–DC Converter With All-Digital Ripple Mitigation Technique

Abstract: This paper presents an adaptive all-digital ripple mitigation technique for fully integrated capacitive dc-dc converters. Ripple control is achieved using a two-pronged approach where coarse ripple control is achieved by varying the size of the bucket capacitance, and fine control is achieved by charge/discharge time modulation of the bucket capacitors used to transfer the charge between the input and output, both of which are completely digital techniques. A dual-loop control was used to achieve regulation and ripple control. The primary single-bound hysteretic control loop achieves voltage regulation and the secondary loop is responsible for ripple control. The dual-loop control modulates the charge/discharge pulse width in a hysteretic variable-frequency environment using a simple digital pulse width modulator. The fully integrated converter was implemented in IBM's 130-nm CMOS process. Ripple reduces from 98 to 30 mV, when ripple control secondary loop is enabled for a load of 0.3 V and 4 mA without significantly impacting the converter's core efficiency. Measurement results show constant ripple, independent of output voltage. The converter achieves a maximum efficiency of 70% for Vin= 1.3 V and Vout= 0.5 V and a maximum power density of 24.5 mW/mm2, including the areas for the decoupling capacitor. The maximum power density increases to 68 mW/mm2 if the decoupling capacitor is assumed to be already present as part of the digital design.

Analysis of dc-link capacitor current in three-level neutral point clamped and cascaded H-bridge inverters

Abstract: Dc-link capacitor sizing is a critical aspect of inverter design. This study investigates capacitor sizing for three-level neutral-point-clamped and cascaded H-bridge inverters, based on an analysis of dc-link capacitor current. Methods used to derive expressions for the root-mean-square (rms) value and harmonic spectrum of the capacitor current in two-level inverters, are extended to the three-level inverters. A new numerical approach is also proposed for calculating the capacitor rms current and voltage ripple. MATLAB code is given for the proposed approach, which can be easily adapted to different modulation strategies and applied to higher-level inverters. Capacitor sizing parameters derived according to this approach are presented for a number of common modulation strategies and are used to compare the requirements of the examined three-level topologies. Results are validated by simulations using MATLAB-Simulink.

Single-phase PWM rectifier with power decoupling ripple-port for double-line-frequency ripple cancellation

Abstract: This paper proposes a new technique for double-frequency ripple-power decoupling in a single-phase PWM rectifier that does not require an electrolytic capacitor, which improves the reliability of the system for long-life applications such as LED lighting. A ripple-port is added in parallel with the output of the PWM rectifier to filter the double-line-frequency ripple using the minimum capacitance necessary for power buffering. Hence, a very small, highly reliable film capacitor is used, which will improve the reliability dramatically compared to the bulky electrolytic capacitor option, which increased the power density of the system. The proposed topology doubles the MTBF increases the lifetime by one order of magnitude. Moreover, the design and control of the ripple-port is independent from the PWM rectifier circuit, so it can be dropped in as an auxiliary circuit to an existing design.

A sub-module capacitor voltage balancing scheme for the Alternate Arm Converter (AAC)

Abstract: A per-phase sub-module capacitor voltage balancing scheme for the Alternate Arm Converter (AAC) is proposed. Leg balancing regulates the sum of sub-module capacitor voltages in a leg to its set-point. Arm balancing regulates each sub-module capacitor voltage to the nominal sub-module capacitor voltage. Additional converter control requirements and the modulation scheme are also discussed. The control and modulation scheme has been verified by simulation. The leg balancing control loop was designed to be critically damped to primarily limit oscillations in the output variable caused by changes in AC-side power demands; the simulation results indicated this specification was met.

Integrated decoupling capacitor employing conductive through-substrate vias

Abstract: A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

Bridgeless electrolytic capacitor-less valley-fill AC/DC converter for offline twin-bus light-emitting diode lighting application

Abstract: To match the key features of light-emitting diode (LED) lighting source and further save power, LED lighting driver also requires long life, while maintaining high efficiency, high power factor, pulse-width modulation dimming and low cost. However, a typical LED lighting driver has the following drawbacks: (i) utilise bulky electrolytic capacitor as storage capacitor with short lifetime; (ii) employ a low-frequency diode bridge as the rectifier cell; and (iii) engage multiple stages cascade structure for multiple LED strings. To overcome the aforementioned shortages, this study proposed a bridgeless electrolytic capacitor-less AC/DC converter for offline LED lighting application. In the proposed converter, the conventional diode rectified bridge is replaced by Totem-pole bridgeless configuration for reducing the number of semiconductors in the line-current path. Meanwhile, the valley-fill circuit is introduced to further reduce the capacitor size. As comparison to its counterpart, the proposed circuit requires only one quarter of the capacitor energy when considering the energy amount (CV 2 ) as the capacitor sizing criterion. Furthermore, the isolation type of the studied circuit is compatible with Twin-Bus configuration for achieving higher overall system efficiency. Finally, the experimental results, taken from a laboratory prototype rated at 50 W, are presented to verify the effectiveness of the proposed converter.

A Power-Efficient Wireless Capacitor Charging System Through an Inductive Link

Abstract: A power-efficient wireless capacitor charging system for inductively powered applications has been presented. A bank of capacitors can be directly charged from an ac source by generating a current through a series charge injection capacitor and a capacitor charger circuit. The fixed charging current reduces energy loss in switches, while maximizing the charging efficiency. An adaptive capacitor tuner compensates for the resonant capacitance variations during charging to keep the amplitude of the ac input voltage at its peak. We have fabricated the capacitor charging system prototype in a 0.35-μm 4-metal 2-poly standard CMOS process in 2.1 mm2 of chip area. It can charge four pairs of capacitors sequentially. While receiving 2.7-V peak ac input through a 2-MHz inductive link, the capacitor charging system can charge each pair of 1 μF capacitors up to ±2 V in 420 μs, achieving a high measured charging efficiency of 82%.

Capacitor and battery combination

Abstract: This disclosure provides systems, methods and apparatus for a combined battery/capacitor energy storage device. The device includes a first device terminal, a second device terminal, a battery connected between the first terminal and the second terminal, and a capacitor connected in parallel with the battery. In one aspect, a rectifier is connected between the first terminal and the capacitor, the rectifier configured to allow substantially unidirectional current flow from the first terminal to the capacitor, in another aspect, a switch is between the capacitor and the first terminal, in another aspect, a current limiter extends between the first terminal and the capacitor. In another aspect, the device includes a housing that includes an integrated battery housing portion and a capacitor housing portion, in another aspect, a bus bar system electrically connects the battery, the capacitor, and the terminals.

Backup power source device and automobile equipped with same

Abstract: A backup power source device includes the following elements: a capacitor; a charging circuit provided in the charging path of the capacitor and performing step-down operation; a boost circuit provided in the output path of the capacitor; and a door-lock-releasing output terminal connected to the boost circuit.

Design of high voltage capacitor charger with improved efficiency, power density and reliability

Abstract: This paper describes the design of a 48 kJ/s high-voltage capacitor charging power supply (CCPS), focusing on its efficiency, power density, and reliability On the basis of a series-parallel resonant converter (SPRC) that provides high efficiency and high power density owing to its soft-switching, the design of the CCPS is explained in detail, including its input filter, resonant tank parameters, high-voltage transformer and rectifier, as well as its protection circuit By using two resonances per switching cycle, which provides a trapezoidal instead of a sinusoidal waveform of the resonant current, the proposed CCPS can take advantage of the lower conduction loss and reduced switching loss by improving the crest factor and allowing a higher value of the snubber capacitor, respectively In addition, the compact design of an input filter without bulky components such as a DC reactor and an electrolytic capacitor allows for high power density, a high power factor, and low cost In addition, the control loops for the voltage and current were optimized with a fast response time in order to compensate for the low frequency ripple of the input voltage, which results from the reduced filter component Experiments on the developed charger were carried out with both resistor and capacitor loads in order to measure not only its efficiency and power factor with respect to the output power but also its charging time, in order to estimate the average charging current The experimental results obtained with a resistor load showed a maximum efficiency of 96% and a power factor of 096 for a full-load condition For the measured charging time of a 4 mF capacitor, with 968 s for 10 kV charging, the average charging current was estimated as 413 A Moreover, to verify the reliability of the developed CCPS, a variety of tests, including opening and shorting of the output terminal as well as misfiring of the discharge switch during the charging operation, were performed with a 200 kJ pulsed power system Finally, it was experimentally confirmed that the developed CCPS shows high performance in terms of efficiency (96 %), power factor (096), and reliability with a high power density (820 W/L)

A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS

Abstract: A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14KB register file (RF) load with an area overhead of 3.6% is demonstrated in 22nm tri-gate CMOS. The all-digital, multi-conversion-mode SCVR provides a wide output voltage range of 0.45-1V from a fixed input voltage of 1.225V. It achieves 63-84% conversion efficiency and supports a maximum load current density of 0.88 A/mm2.

Double-tiered switched capacitor battery charge equalizer with chain structure

Abstract: The switched capacitor equalizer is one of the simplest voltage equalizing methods. However this equalizer has disadvantages which are prolonged equalization time and large difference of equalization time caused by the position of problematic energy storage cell. This paper proposes novel switched capacitor equalizer which has the advantages of the switched capacitor with chain structure and the double-tiered switched capacitor. The proposed circuit has many paths of charge exchange, which reduces the equalization time and constantly keeps the performance above a certain level regardless of the position of the problematic cell. The performance of the proposed circuit was confirmed with simulation and circuit experiments.

V 2 control with capacitor current ramp compensation using lossless capacitor current sensing

Abstract: V2 control is a popular control architecture in point-of-load Buck converters due to its simplicity and fast transient response. V2 control with ceramic capacitor has instability issue. This paper reviews the existing solutions and their limitations are studied. A solution using output capacitor current ramp to stabilize the control loop is proposed. The analog capacitor current sensing method based on impedance match is used in the implementation of lossless current sensing. A small signal equivalent circuit is proposed for the analysis of the proposed control method. The proposed solution is superior to existing compensation methods for the excellent transient response for a wide range of duty cycle. The effectiveness of the concept and implementation are verified by experimental results.

One-inductor-based auxiliary circuit for dc-link capacitor voltage equalisation of diode-clamped multilevel converter

Abstract: The one-inductor-based auxiliary balancing circuit is proposed to equalise dc-link capacitor voltages of diode-clamped multilevel converters (DCMC) in this study. After theoretical analysis of balancing unit in traditional one-level-based balancing schemes, one-inductance-based schemes are designed according to the same operating principle. Via some conducted diodes and switches by simple control, this circuit provides energy exchange paths of all the dc-link capacitors by only one inductor. Firstly, the inductor absorbs energy from the capacitor with the highest voltage. Then, this capacitor is discharged and its voltage will decrease. Secondly, the inductor releases energy to the capacitor with the lowest voltage. Then, this capacitor is charged and its voltage will increase. After performing this operation a number of times, all the voltages of the dc-link capacitors will finally reach the same value. The circuit configurations, conducting paths and control strategies of one-inductor-based scheme for five-level DCMC are analysed, respectively. Owing to small equivalent resistances of capacitor and inductor, the small power loss could be achieved. Simulations and experiments have been carried out. The steady-state and dynamic results verify the effective balancing performance of this circuit.