Showing papers on "Decoupling capacitor published in 2015"

Power Decoupling Method for Single-Phase H-Bridge Inverters With No Additional Power Electronics

Abstract: An active method for double-frequency power ripple decoupling in single-phase inverters is presented in this paper, exhibiting the main advantage of not using additional power semiconductors besides the H-bridge. The proposed method requires only two capacitors placed between the midpoint and one end of each inverter leg. An original control solution of the inverter ensures the power ripple transfer toward the two decoupling capacitors without affecting the inverter output voltage. The simple design makes the proposed solution easy to adapt for single-phase inverters in H-bridge configuration. This paper focuses on the autonomous operation mode of the inverter, detailing its operating principle and the control analysis. The system performances, including the impact of the decoupling circuit on the inverter efficiency, are assessed by means of experimental results.

Seventeen-Level Inverter Formed by Cascading Flying Capacitor and Floating Capacitor H-Bridges

Abstract: A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation.

MMC Capacitor Voltage Decoupling and Balancing Controls

Abstract: A modular multilevel converter control system, based on converter energy storage, is proposed in this paper for two different control modes: active power and dc voltage. The proposed control system decouples the submodule (SM) capacitor voltages from the dc bus voltage. One of the practical applications is the management of active redundant SMs. A practical HVDC system with 401-level MMCs, including 10% redundancy in MMC SMs, is used for validating and demonstrating the advantages of the proposed control system. This paper also presents a novel capacitor voltage balancing control based on $\max$ – $\min$ functions. It is used to drastically reduce the number of switchings for each SM and enhances computational efficiency.

DC Capacitor-Less Inverter for Single-Phase Power Conversion With Minimum Voltage and Current Stress

Abstract: Single-phase power conversion such as pulse width modulation rectifier, grid connected PV inverter system, static synchronous compensator all can be implemented by an H-bridge inverter and a large electrolytic dc capacitor to absorb the ripple power pulsating at twice the line frequency (2ω ripple power) This paper proposed a dc capacitor-less inverter for H-bridge with minimum voltage and current stress By adding another phase leg to control an ac capacitor, the 2ω ripple power can be absorbed by the capacitor and theoretically 2ω ripples to the dc capacitor can be eliminated completely The H-bridge and the addition phase leg can be analyzed together as an unbalanced three phase system By adopting space-vector pulse width modulation control and choosing the optimum ac capacitance and the voltage reference, the voltage and current stress of the switches can be minimized to the same as the conventional H-bridge The size of capacitor is reduced by ten times compared to the conventional H-bridge system Simulation and experimental results are shown to prove the effectiveness of the proposed dc capacitor-less inverter and active power decoupling method

Fast Sorting Method for Balancing Capacitor Voltages in Modular Multilevel Converters

Abstract: The modular multilevel converter (MMC) is attracting more and more interest in high-power and high-voltage applications. Highly redundant, each arm of the converter is made of a large number of identical submodules with inner storage capability allowing to reach very high voltage without dc-link capacitor. The control of such a converter represents a challenge when it comes to the implementation of an MMC with a large number of submodules, namely in distributing the control tasks and handling the communicated values in-between controllers and submodules. This paper presents the details of an innovative submodule selection method for the submodule capacitor's voltage balancing within one arm of an MMC. “The Tortoise and the Hare” sorting method shows very fast response, high reliability, and its implementation suits a large number of implemented submodules as for high-voltage dc applications. The proposed submodule capacitor's balancing method is validated on a three-phase 10-kVA prototype with five submodules per arm.

Two-Stage Power Conversion Architecture Suitable for Wide Range Input Voltage

Abstract: This paper presents a merged-two-stage circuit topology suitable for either wide-range dc input voltage or ac line voltage at low-to-moderate power levels (e.g., up to 30 W). This two-stage topology is based on a soft-charged switched-capacitor preregulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect current control are used to maintain high efficiency, high power density, and high power factor. The proposed architecture is applied to an LED driver circuit, and two implementations are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 88%-96% efficiency at 30-W power across 25-200-V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4-W average power. Contributions of this paper include: 1) demonstrating the value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems; 2) introduction of a multimode soft-charged SC stage for the merged architecture that enables compression of an 8:1 input voltage range into a 2:1 intermediate range, along with its implementation, loss considerations, and driving methods; and 3) merging of this topology with an resonant transition discontinuous-mode inverted buck stage and pseudocurrent control to enable step-down power conversion (e.g., for LED lighting) operating at greatly increased frequencies and reduced magnetics size than with more conventional approaches.

A Modified Modular Multilevel Converter With Reduced Capacitor Voltage Fluctuation

Abstract: The requirement of a large number of sizeable capacitors in traditional modular multilevel converter (MMC) submodules is seen as a major barrier hampering its widespread use in medium-voltage applications. To reduce the value of capacitance, this paper presents a modified MMC (M-MMC) topology, which offers inherent alleviated capacitor voltage fluctuations compared with traditional MMC. Its operating principle, modulation, and capacitor voltage balancing strategies are described in detail. Moreover, a novel capacitor voltage fluctuation suppression scheme is also proposed to further reduce the second-order capacitor voltage ripples. Finally, both a three-phase prototype of M-MMC and traditional MMC have been built in the laboratory. The effectiveness of the proposed M-MMC topology and control methods is experimentally verified by comparing with the traditional MMC.

A High-Efficiency Resonant Switched Capacitor Converter With Continuous Conversion Ratio

Abstract: A resonant switched capacitor converter with high efficiency over a wide and continuous conversion ratio range is introduced. The efficiency of the topology depends primarily on the conduction losses and is decoupled, to a large extent, from the voltage conversion ratio. This is an advantage over classical switched capacitor converters, for which the efficiency is strongly related to the conversion ratio. The operation principle applies three zero current switching states to charge, discharge, and balance the remaining charge of the flying capacitor. This results in a gyrator, i.e., a voltage-dependent current source, with a wide range of voltage conversion ratios (smaller as well as greater than unity) as well as bidirectional power flow capabilities. The analytical expressions for the conversion ratio and expected efficiency are provided and validated through simulations and experiments. The experimental verifications of the converter demonstrate peak efficiency of 96% and above 90% efficiency over a wide range of voltage gains and loading conditions. In addition, the system was found to be highly efficient at the extreme cases of both light and heavy loads.

A Current-Sensorless Online ESR and C Identification Method for Output Capacitor of Buck Converter

Abstract: As electrolytic capacitor is apt to fail in power circuits, it is very important to identify its electrical parameters, mainly the equivalent series resistance (ESR) and capacitance ( C ). A noninvasive online identification method of capacitor's ESR and C for continuous-conduction-mode (CCM) buck converter is proposed in this paper. Based on the ac component of capacitor voltage, the calculation model is founded. By sampling the pulse width modulation signal and output voltage, the method needs no current sensor and is effective for the CCM buck converter operating at different conditions. Implementation of the identification system is presented. The tests are carried out for different aged capacitors and ambient temperatures. The experimental results validate the effectiveness of the method.

A 3-Phase Resonant Switched Capacitor Converter Delivering 7.7 W at 85% Efficiency Using 1.1 nH PCB Trace Inductors

Abstract: In recent years, there has been a push towards high-density and monolithic DC-DC converters to support applications such as performance and mobile computing, consumer electronics, and renewable energy. Switched capacitor (SC) converters have started to gain traction for a number of these applications, but are still subject to fundamental limitations that drive them towards expensive process options and high switching frequencies. Variable regulation is challenging with the SC approach, and comes at the cost of lower power density and efficiency. This work presents a resonant switched capacitor (ReSC) topology that addresses some of these challenges by introducing a small amount of inductance in series with the flying capacitor, eliminating charge-sharing losses and thus allowing efficient operation in a low-cost process option. The three-phase interleaved topology can deliver up to 7.7 W at 85% efficiency (power density of 0.91 W/mm $^{2}$ or 6.4 kW/in $^{3}$ ) using a bootstrapped n-channel power train and single-digit nH inductors embedded in a flip-chip assembly. We also present the first implementation of efficient, fully-variable conversion ratios in a silicon ReSC integrated circuit without reconfiguration or gain-hopping .

DPA, Bitslicing and Masking at 1 GHz

Abstract: We present DPA attacks on an ARM Cortex-A8 processor running at 1 GHz. This high-end processor is typically found in portable devices such as phones and tablets. In our case, the processor sits in a single board computer and runs a full-fledged Linux operating system. The targeted AES implementation is bitsliced and runs in constant time and constant flow. We show that, despite the complex hardware and software, high clock frequencies and practical measurement issues, the implementation can be broken with DPA starting from a few thousand measurements of the electromagnetic emanation of a decoupling capacitor near the processor. To harden the bitsliced implementation against DPA attacks, we mask it using principles of hardware gate-level masking. We evaluate the security of our masked implementation against first-order and second-order attacks. Our experiments show that successful attacks require roughly two orders of magnitude more measurements.

A Reconfigurable Dual-Output Switched-Capacitor DC-DC Regulator With Sub-Harmonic Adaptive-On-Time Control for Low-Power Applications

Abstract: This paper presents a reconfigurable switched-capacitor (SC) DC-DC regulator to simultaneously generate two different regulated output voltages for low-power applications. With capacitor and power switch sharing in the power stage, the area efficiency of the proposed regulator is improved. The proposed power stage can also be configured to provide different conversion ratios in order to maintain high power efficiency of the regulator in different input voltages. A sub-harmonic adaptive-on-time (SHAOT) control scheme is developed to regulate both outputs. The adaptive-on-time control automatically adjusts the durations of charge transfer to both outputs to reduce output voltage ripples under different input voltages. Switching power transistors at the fundamental or sub-harmonics of the system clock frequency can provide predictable noise spectrum to both regulated outputs and improve the light-load regulator power efficiency. The cross regulation between both outputs can also be minimized by the proposed SHAOT scheme. Implemented in a standard 0.35 μm CMOS process, the proposed regulator provides two regulated outputs of 2 V and 3 V and delivers up to 12 mA at each output. The proposed regulator achieves a maximum power efficiency of 89.5%. Both power efficiency and output ripple can be improved by 10% and ~ 4 times, respectively, over a wide input range from 1.1 V to 1.8 V by using the proposed reconfigurable power stage and adaptive-on-time scheme.

MMC capacitor voltage decoupling and balancing controls

Abstract: A Modular Multilevel Converter (MMC) control system based on converter energy storage is proposed in this paper for two different control modes: active power and dc voltage. The proposed control system decouples the sub-module (SM) capacitor voltages from the dc bus voltage. One of the practical applications is the management of active redundant SMs. A practical HVDC system with 401-level MMCs including 10% redundancy in MMC SMs, is used for validating and demonstrating the advantages of the proposed control system. This paper also presents a novel capacitor voltage balancing control based on max-min functions. It is used to drastically reduce the number of switchings for each SM and enhances computational efficiency.

An Online Monitoring Scheme of DC-Link Capacitor's ESR and C for a Boost PFC Converter

Abstract: As electrolytic capacitor is apt to fail in power converters, it is very important to monitor its electrical parameters, mainly the equivalent series resistance (ESR) and capacitance (C). A novel non-invasive online monitoring method of DC-link capacitor's ESR and C for boost power factor correction (PFC) converter is proposed in this paper. By analyzing the capacitor voltage ripple which is composed of that of ESR and C, the calculation model is founded, which shows that instead of additional current sensor, only two values of capacitor voltage in particular moments within a line cycle need to be sampled for the calculation of ESR and C. The schematic of the monitoring system together with the design considerations of the trigger circuit, the isolated voltage amplifier, the isolated current amplifier are described in detail. The experimental results show the effectiveness of the method.

Grid-Connected Forward Microinverter With Primary-Parallel Secondary-Series Transformer

Abstract: This paper presents a primary-parallel secondary-series multicore forward microinverter for photovoltaic ac-module application. The presented microinverter operates with a constant off-time boundary mode control, providing MPPT capability and unity power factor. The proposed multitransformer solution allows using low-profile unitary turns ratio transformers. Therefore, the transformers are better coupled and the overall performance of the microinverter is improved. Due to the multiphase solution, the number of devices increases but the current stress and losses per device are reduced contributing to an easier thermal management. Furthermore, the decoupling capacitor is split among the phases, contributing to a low-profile solution without electrolytic capacitors suitable to be mounted in the frame of a PV module. The proposed solution is compared to the classical parallel-interleaved approach, showing better efficiency in a wide power range and improving the weighted efficiency.

Automatic current sharing mechanism in the series capacitor buck converter

Abstract: This study examines the mechanism and effectiveness of current sharing in a multiphase, series capacitor buck converter. The automatic current sharing mechanism is inherent to the series capacitor buck topology and uniquely utilizes its series capacitor. Unlike conventional multiphase buck converters, current sharing is achieved without any current sensing circuits or added external control loops. Analysis of the automatic current sharing mechanism explains its robustness to variations in inductance, dc resistance (DCR), and temperature. Unequal control switch on-times are found to have measurable impact on sharing accuracy. Results from a two-phase, 12 V input, 10 A output hardware prototype demonstrate the simple, highly accurate current sharing capabilities of the series capacitor buck converter. Experimental results for unequal on-times exhibit unmatched average currents but stable operation with a dc offset.

Isolated AC/DC Offline High Power Factor Single-Switch LED Drivers Without Electrolytic Capacitors

Abstract: Energy-efficient residential lighting such as household light-emitting diode (LED) lamps with ac input require an ac/dc converter (or driver) with large output capacitance to minimize the low frequency LED current ripple. The energy storage capacitor used in the conventional ac/dc LED driver is usually an electrolytic capacitor due to its low cost and high energy density. However, the average lifetime of an electrolytic capacitor is at least 2–3 times less than that of an LED device. Hence, the potential lifetime of the LED lamp is significantly affected by the presence of the electrolytic capacitor in the driver circuit. In this paper, two novel isolated single-switch ac/dc high power factor LED drivers without using any electrolytic capacitors are proposed. In the proposed circuits, the energy storage capacitor is moved to the rectifier side, with a three-winding transformer used to provide isolation; input power factor correction as well as to store and provide the required energy to the output. As a result, the energy storage capacitance is significantly reduced, which allows film capacitor to be used to replace the conventionally used electrolytic capacitors. The circuit’s operating principles and its characteristics are described in this paper. Simulation and experimental results are given on a 120 $\text{V}_{\rm rms}$ , 12 W prototype to confirm that a power factor of at least 0.96 is achieved.

A high-efficiency high energy density buffer architecture for power pulsation decoupling in grid-interfaced converters

Abstract: A high-efficiency high-energy-density buffer architecture is proposed for power pulsation decoupling in power conversion between DC and single phase AC. We present an active decoupling solution that yields improved efficiency and reduced circuit complexity compared to existing solutions. By connecting a buffer converter in series with the main decoupling capacitor, the main capacitor is allowed larger ripple for improved energy utilization (and thus much reduced volume), while the DC bus voltage is maintain close to ripple free. The buffer converter has low voltage stress and is only processing a small fraction of the total power of the entire architecture, allowing a very small active circuit volume and very high system efficiency. A control scheme is proposed to exploit the small remaining bus ripple to compensate the power loss in the power converter and balance the power cycle of the buffer architecture. A 2 kW hardware prototype has been built to demonstrate the benefit of the proposed solution. The hardware prototype achieves 20 times capacitance reduction and 2 times overall volume reduction compared to the conventional passive decoupling solution. An energy density of 110 W/inch3 and an efficiency above 98.7% across a wide load range has been experimentally verified.

Single-phase current source converter with power decoupling capability using a series-connected active buffer

Abstract: This study proposes a new power decoupling circuit applied to the single-phase current source converter (SCSC). Differing from the existing power decoupling technologies, the proposed power decoupling circuit could be viewed as a controlled voltage source in series with the DC inductor, and work with SCSC independently. That facilitates the separate design of the modulation schemes and the control algorithms for the power decoupling circuit and SCSC, and reduces the operation restrictions imposed by requirements. The fundamental principle of the proposed converter is analysed, and the voltage reference requirement for the buffer capacitor is investigated. To guarantee high input current quality of SCSC, a control method, where the input current is treated as a virtual control input, is proposed. Finally the effectiveness of this topology is verified by the simulations and experimental results.

A Simple Differential Mode EMI Suppressor for the $LLCL$ -Filter-Based Single-Phase Grid-Tied Transformerless Inverter

Abstract: The single-phase power converter topologies evolving of photovoltaic applications are still including passive filters, like the $LCL$ - or $LLCL$ -filter. Compared with the $LCL$ -filter, the total inductance of the $LLCL$ -filter can be reduced a lot. However, due to the resonant inductor in series with the bypass capacitor, the differential mode (DM) electromagnetic interference (EMI) noise attenuation of an $LLCL$ -filter-based grid-tied inverter declines. Conventionally, a capacitor was inserted in parallel with the $LC$ resonant circuit branch of the $LLCL$ -filter to suppress the DM EMI noise. In order to achieve a small value of capacitor as well as to minimize the additional reactive power, a novel simple DM EMI suppressor for the $LLCL$ -filter-based system is proposed. The characters of two kinds of DM EMI suppressor are analyzed and compared in detail. Simulations and experiments on a 0.5-kW 110-V/50-Hz single-phase grid-tied inverter prototype are accomplished to confirm the analysis.

A Modified Three Phase Four-Wire UPQC Topology with Reduced DC-Link Voltage Rating

Abstract: 2 ABSTRACT: This circuit consists of capacitor in series with the interfacing inductor of the shunt active filter. The series capacitor enables reduction in dc-link voltage requirement of the shunt active filter and simultaneously compensating the reactive power required by the load, so as to maintain unity power factor, without compromising its performance. This allows us to match the dc-link voltage requirements of the series and shunt active filters with a common dc link capacitor. Further, in this topology, the system neutral is connected to the negative terminal of the dc bus.. This will avoid the requirement of the fourth leg in VSI of the shunt active filter and enables Independent control of each leg of the shunt VSI with single dc capacitor. The topology uses a capacitor in series with the interfacing inductor of the shunt active filter, and the system neutral is connected to the negative terminal of the dc-link voltage to avoid the requirement of the fourth leg in the voltage source inverter (VSI) of the shunt active filter. The average switching frequency of the switches in the VSI also reduces, consequently the switching losses in the inverters reduce. Detailed design aspects of the series capacitor and VSI parameters have been discussed in the paper. A simulation study of the proposed topology has been carried out using PSCAD simulator, and the results are presented. Experimental studies are carried out on three-phase UPQC prototype to verify the proposed topology.

System and Method for a Startup Cell Circuit

Abstract: According to an embodiment, a circuit comprising includes a first switching circuit coupled to a power supply input, a second switching circuit coupled to an output of the first switching circuit, a supply capacitor coupled to the second switching circuit, and a startup cell coupled to the power supply input and the supply capacitor. The startup cell is configured to electrically couple the power supply input to the supply capacitor when the second switching circuit is not actively switching. The startup cell is also configured to electrically decouple the power supply input from the supply capacitor when the second switching circuit is actively switching.

A W-Band High-Efficiency CMOS Differential Current-Reused Frequency Doubler

Abstract: A W-band differential frequency doubler using a current-reuse configuration in a 65 nm CMOS process is presented in this letter. The differential current-reuse circuit with a second harmonic coupling transformer is introduced to improve conversion gain at small input powers minimizing the effect of the RF bypass capacitor. The proposed circuit achieves a conversion gain of $0.8\sim -4.2~{\rm dB}$ and a fundamental rejection above 19 dB in the input frequency range of 36.5~44 GHz with $-4 ~{\rm dBm}$ input power. It has conversion gain variation below 1 dB when the input power varies from $-7.4$ to 0.1 dBm at 77 GHz. The dc power consumption is 14 mW. It has the highest conversion gain with the smallest chip size of 0.22 ${\rm mm}^{2}$ among all V-/W-band CMOS frequency doublers.

Instantaneous thermal modeling of the DC-link capacitor in PhotoVoltaic systems

Abstract: Capacitors have been witnessed as one of the weak points in grid-connected PhotoVoltaic (PV) applications, and thus efforts have been devoted to the design of reliable DC-link capacitors in PV applications. Since the hot-spot temperature of the capacitor is one of the failure inducers, instantaneous thermal modeling approaches considering mission profiles for the DC-link capacitor in single-phase PV systems are explored in this paper. These thermal modelling approaches are based on: a) fast Fourier transform, b) look-up tables, and c) ripple current reconstruction. Moreover, the thermal modelling approaches for the DC-link capacitors take into account the instantaneous thermal characteristics, which are more challenging to the capacitor reliability during operation. Such instantaneous thermal modeling approaches enable a translation of instantaneous capacitor power losses to capacitor thermal loading from the operating conditions. As a consequence, it offers new insights into the temperature monitoring and reliability-oriented design of the DC-link capacitors, and thus a more reliable operation of single-phase grid-connected PV systems can be enhanced. Study results on a 3-kW single-phase grid-connected PV system have been adopted to demonstrate a look-up table based modelling approach, where real-field daily ambient conditions are considered.

High-performance quasi-Z-source inverter with low capacitor voltage stress and small inductance

Abstract: A high-performance quasi-Z-source inverter (qZSI) is presented in this study. The proposed circuit has the four advantages: (i) reduction in voltage stress across the Z-network capacitor, (ii) voltage source and inverter bridge share the same ground point, (iii) reduced inrush current during start-up, (iv) wide range of load operation even with a small inductance in the Z-network. The proposed qZSI can be controlled as the traditional ZSI. This study analyses the operation principle of the proposed circuit and carries out its parameter design. Finally, experimental results are presented to validate the operation of the proposed qZSI.

Techniques of Dual-Path Error Amplifier and Capacitor Multiplier for On-Chip Compensation and Soft-Start Function

Abstract: Techniques of a dual-path error amplifier and two capacitor multipliers for providing on-chip frequency compensation and soft-start function are proposed in this paper. The concept of the dual-path error amplifier is to use two currents to charge and discharge a compensation capacitor simultaneously. As a result, the equivalent capacitance is enlarged significantly with little additional power and silicon area. The dc-dc converter with the dual-path architecture also has great performance in transient response because the compensation capacitor is reduced significantly. For the soft-start function, the subtractive-type and time-average capacitor multipliers are used to relax the restriction of the capacitance and the charging current. Consequently, it is easy to integrate the soft-start capacitance into a chip and the output overshoot voltage can be suppressed. A prototype converter fabricated with TSMC 0.35-μm 2P4M CMOS process verifies the effectiveness of the techniques of a dual-path error amplifier and two capacitor multipliers. Experimental results demonstrate the converter stability, transient response, and soft-start function. The transient recovery time and transient ripple are less than 20 μs and 25 mV, respectively, for the load current swing from 50 to 500 mA. Moreover, the soft-start time is up to 8 ms. With the proposed techniques, the external pins of the dc-dc converters are minimized and their performance is improved significantly.

The direct-conversion resonant switched capacitor architecture with merged multiphase interleaving: Cost and performance comparison

Abstract: Switched capacitor and resonant switched capacitor topologies have gained interest in recent years for highly integrated (monolithic) DC-DC converters, and more generally for a range of applications that require high density, high efficiency, and low cost. This work presents experimental and theoretical results for a new resonant topology that has architectural similarity to the more common 3-level buck converter. We further outline the prospects of using merged-interleaving to reduce voltage ripple while maximizing the utilization of passive components. We present the results of an experimental prototype that can be configured as a switched capacitor, resonant switched capacitor, or resonant 3-level topology. Importantly, by constraining factors such as total cost of active and passive components, volumetric energy density, and other design factors, we attempt to provide a fair comparison of the respective converter prototypes for applications spanning DC power delivery, and power management for renewable energy applications such as photovoltaics and battery management.

Capacitor aging detection in DC-DC converter output stage

Abstract: One of the largest reliability issues in switching mode power supplies is capacitor aging based degradation. This paper proposes a step excitation based online capacitor wear-out detection method for output stage capacitor of a step down DC-DC converter. Changes in the converter output voltage dynamics are detected during operation by analyzing output voltage step response. Sensitivity of the presented method is evaluated with respect to component variations in converter main circuit. The feasibility of presented method is verified with experimental tests using a converter prototype. The results show, that the presented method is practical and adequate method for online capacitor degradation detection in various operating conditions.

Capacitor aging detection for the DC filters in the power electronic converters using ANFIS algorithm

Abstract: DC filters are responsible for more than half of the failures in the power electronic converters. One approach to improving the reliability and maintainability of the converters is to include failure diagnosis for the DC filters within the power converter. DC filters failures may be classified as sudden faults which may take the form of breakdown faults resulting from a blown capacitor fuse and gradual faults caused by capacitor aging. This paper presents a fault detection and location for the capacitor aging faults in the DC filters of the power converters. The proposed fault diagnosis is based on the adaptive neuro-fuzzy inference system (ANFIS) algorithm. The inputs to the ANFIS unit are only the input voltage of the converter as well as the voltages across the DC filters. The output of the ANFIS unit is utilized as an index in order to identify the capacitor aging fault in the power converter. Then, it locates the fault within the two DC filters installed in the power converter.

Apparatus and methods for variable capacitor arrays

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.