Showing papers on "Decoupling capacitor published in 2018"

Distributed Control for a Modular Multilevel Converter

Abstract: Conventional centralized control strategies may reduce the flexibility and expandability of a modular multilevel converter (MMC) system. To tackle this issue, this paper proposes a distributed control architecture that is capable of assigning certain control tasks to distributed local controllers and improves the modularity of an MMC system. A central controller dealing with the output current regulation based on sensed arm currents is adopted. The control of MMC internal dynamics and the pulsewidth modulation (PWM) generation are distributed into local controllers. Unlike the conventional MMC control that needs all submodule capacitor voltages for capacitor voltage averaging, the proposed capacitor voltage control only relies on local submodule voltage measurement. Consequently, communication-intensive capacitor voltage transmission in each control cycle is not required and the communication burden of the control system can be significantly reduced. The control loops and possible control conflicts among submodules are presented and considered for system stability analysis. The effectiveness of the proposed distributed control architecture and capacitor voltage control for an MMC are confirmed by the start-up, steady state, and transient experimental results.

High Step-Up DC–DC Converter Based on Switched Capacitor and Coupled Inductor

Abstract: Due to the relatively low output voltage of photovoltaic (PV) source, a high step-up converter with high efficiency is needed when the PV source is connected to the power grid. A novel high step-up converter based on two switched capacitors and a coupled inductor is proposed in this paper. The operating principle is analyzed and the voltage gain is derived. A 100-W prototype is fabricated in the laboratory to verify the theoretical analysis, and the highest efficiency is 96.4%.

A Low-Flicker-Noise 30-GHz Class-F 23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path

Abstract: This paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3- to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of −106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of −184 dBc/Hz at 27.3 GHz. Its flicker phase-noise ( $1/f^{3}$ ) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

Development of DC to Single-Phase AC Voltage Source Inverter With Active Power Decoupling Based on Flying Capacitor DC/DC Converter

Abstract: In the present, a power decoupling method without additional component is proposed for a dc to single-phase ac converter, which consists of a flying capacitor dc/dc converter (FCC) and the voltage source inverter (VSI). In particular, a small flying capacitor in the FCC is used for both a boost operation and a double-line-frequency power ripple reduction. Thus, the dc-link capacitor value can be minimized in order to avoid the use of a large electrolytic capacitor. In addition, component design, of, e.g., the boost inductor and the flying capacitor, is clarified when the proposed control is applied. Experiments were carried out using a 1.5-kW prototype in order to verify the validity of the proposed control. The experimental results revealed that the use of the proposed control reduced the dc-link voltage ripple by 74.5%, and the total harmonic distortion (THD) of the inverter output current was less than 5%. Moreover, a maximum system efficiency of 95.4% was achieved at a load of 1.1 kW. Finally, the high power density design is evaluated by the Pareto front optimization. The power densities of three power decoupling topologies, such as a boost topology, a buck topology, and the proposed topology are compared. As a result, the proposed topology achieves the highest power density (5.3 kW/dm3) among the topologies considered herein.

Imbalance Mechanism and Balanced Control of Capacitor Voltage for a Hybrid Modular Multilevel Converter

Abstract: Due to different charging and discharging characteristics of full-bridge submodules and half-bridge submodules in hybrid modular multilevel converters (MMC), capacitor voltage imbalance will occur under boosted ac voltage or reduced dc voltage conditions. To address this issue, the mechanism of capacitor voltage imbalance is carefully studied, with three main factors—modulation index, power angle, and hybridization ratio—summarized and their effect on capacitor voltage imbalance analyzed. Further, a control strategy based on fundamental frequency reactive circulating current injection is proposed to keep the capacitor voltage balanced in the hybrid MMC. The amplitude and phase angle of the injected circulating current are calculated and their influence on the energy fluctuation in the submodules’ capacitors and the semiconductors’ current stress is explored. Experimental results under boosted ac voltage and reduced dc voltage conditions demonstrate the feasibility and validity of the proposed scheme.

Stability Analysis of LCL-Type Grid-Connected Inverter Under Single-Loop Inverter-Side Current Control With Capacitor Voltage Feedforward

Abstract: When single-loop inverter-side current control is used in the LCL -type inverters, there may be more than one stable region with regard to computation delay in control path. The system is stable if computation delay is small enough, but it, named as the first stable region, may be too narrow to finish the control codes in high-frequency system. On the other hand, the second stable region is highly sensitive to the grid impedance variation and is hardly applicable in weak grids. To deal with the situation, this paper investigates the influence of the capacitor voltage feedforward on the system stability considering flexible computation delay in feedforward path. It is found that the capacitor voltage feedforward is able to suppress the resonance of the LCL filter. However, a new resonance may arise if computation delay is not carefully handled. The influence of computation delay in both forward path and feedforward path on system stability is systematically analyzed. The analytical results show that after applying feedforward control with optimized delay, the system stability is greatly improved and is not sensitive to the grid impedance variation. The simulation and experiment results verify the analytical results.

A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control

Abstract: This paper presents a recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude. The proposed RLDO enables a practical digital replacement to analog LDOs by using an SAR-like binary search algorithm in a coarse loop and a sub-LSB pulse width modulation duty control scheme in a fine loop. A proportional-derivative compensation scheme is employed to ensure stable operation independent of load current, the size of the output decoupling capacitor, and clock frequency. Implemented in 0.0023 mm2 in 65 nm CMOS, the 7-bit RLDO achieves, at a 0.5-V input, a response time of 15.1 ns with a figure of merit of 199.4 ps, along with stable operation across a 20 000 $\times $ dynamic load range.

Switched-Capacitor Quasi-Switched Boost Inverters

Abstract: In this paper, two switched-capacitor quasi-switched boost inverters (qSBIs) are proposed. By adding one capacitor and one diode to the qSBIs, the proposed inverters achieve high voltage gain with low voltage stress on active switches, capacitors, and diodes. The proposed inverters can extend to n -cell for voltage gain improvement. The operating principle, steady-state analysis, and impedance parameter selections of the proposed inverter are presented. A full comparison between the proposed inverter and other impedance-source inverters is addressed. A 500-W prototype is built to verify the operating theory of the proposed inverter in both the standalone mode and the grid-connected mode. Simulation and experimental results validate the theoretical analysis.

Overview of micro-inverters as a challenging technology in photovoltaic applications

Abstract: One of the key components of the photovoltaic (PV) system is inverters due to their function as being an operative interface between PV and the utility grid or residential application. In addition, they can be employed as power quality conditioners at the point of common coupling (PCC). It should be noted that in inverter technologies, there has been an increasing interest to achieve robust output power injection capabilities with lesser design complexity in terms of controller part and power circuit topology. Micro-inverters (MIs) are module based type of inverters that have aroused much interest in recent years. Owing to their distributed architecture mounted with individual PV modules, system reliability can be improved remarkably by using MIs. Furthermore, a module based nature of the MI architecture provides a number of advantages, such as low converter power rating, low power losses, accurate maximum power point tracking (MPPT) ability against partially shading conditions and elimination of PV panel mismatches. However, there is still known weighted conversion efficiency of MIs ranges between 90% and 95%. Therefore, novel designs focus on the known weak aspects of traditional MIs and their failure mechanisms. In this paper, state-of-the-art technologies for MIs with a detailed survey on the technical features consisting of power circuit configuration, control structures, grid compatibility abilities, decoupling capacitor placement, energy harvesting capabilities, and safety mechanisms are presented. Additionally, elaborated comparison on MIs topologies is realized and some future research fields on MIs are summarized.

A Switched Capacitor Energy Harvester Based on a Single-Cycle Criterion for MPPT to Eliminate Storage Capacitor

Abstract: A single-cycle criterion maximum power point tracking (MPPT) technique is proposed to eliminate the need for bulky on-chip capacitors in the energy harvesting system for Internet of Everything (IoE). The conventional time-domain MPPT features ultra-low power consumption; however, it also requires a nanofarad-level capacitor for fine time resolution. The proposed maximum power monitoring does not rely on the time-domain, but on logic criterion that can be simply determined by a finite-state machine where the maximum photovoltaic (PV) power occurs at minimum conversion ratio and maximum switching frequency. Single-cycle is used as the criterion to determine the magnitude of the output power. Practical concerns, such as self-startup and self-sustaining capabilities are here addressed by proper design of the reconfigurable switched capacitor power converter. A hysteretic control not only regulates the output, but also avoids the loading condition in IoE applications. This harvester simultaneously addresses the challenges including self-startup, self-sustaining capability, and regulated output without using a storage capacitor. Compared with various PV cells, the power conversion efficiency has a peak value of 72%, which remains above 60% for a wide harvesting voltage and power range. The chip area is as small as 0.552 mm2.

A Novel Method Based on Self-Power Supply Control for Balancing Capacitor Static Voltage in MMC

Abstract: The modular multilevel converter is one of the most attractive converter topologies for high-voltage dc transmission systems, but it needs at least 10 min during the system uncontrolled precharge stage to verify the stability and reliability of submodules (SMs), making the capacitor static voltage balancing a key issue. This paper proposes a novel method based on self-power supply control for balancing capacitor static voltage. Because of the influence of self-power supplies on capacitor voltages, the method can keep the capacitor static voltage balanced by controlling the input characteristic of SMs self-power supplies. The control signals of self-power supplies have a fixed frequency and duty ratio, and they can be determined based on capacitor voltage sorting results and self-power supply output support capacitor. Compared with previous works, this method has less computation, and it does not rely on IGBTs and additional complex circuits except for the self-power supplies. This can save on the software and hardware costs. The proposed method also leads to improved equalizing resistances and reduced active power losses of the SMs. Simulations and experimental studies were conducted, and the results confirm the effectiveness of the proposed method.

Electrical Performance and Reliability Characterization of a SiC MOSFET Power Module With Embedded Decoupling Capacitors

Abstract: Integration of decoupling capacitors into silicon carbide (SiC) metal oxide semiconductor field effect transistor ( mosfet ) modules is an advanced solution to mitigate the effect of parasitic inductance induced by module assembly interconnects. In this paper, the switching transient behavior is reported for a 1.2-kV SiC mosfet module with embedded dc-link capacitors. It shows faster switching transition and less overshoot voltage compared to a module using an identical package but without capacitors. Active power cycling and passive temperature cycling are carried out for package reliability characterization and comparisons are made with commercial Si and SiC power modules. Scanning acoustic microscopy images and thermal structure functions are presented to quantify the effects of package degradation. The results demonstrate that the SiC modules with embedded capacitors have similar reliability performance to commercial modules and that the reliability is not adversely affected by the presence of the decoupling capacitors.

Decoupling Capacitors Placement for a Multichip PDN by a Nature-Inspired Algorithm

Abstract: This contribution deals with the optimal placement of the decoupling capacitances on the gridded power delivery network of a multichip assembly with interposer. The optimization is performed by means of a nature-inspired algorithm of the genetic class. Different placement strategies are considered and compared. The cost function is based on the evaluation of the input impedance looked into the power and ground rails of the power distribution network and its comparison with a user-defined mask.

An Enhanced Steady-State Model and Capacitor Sizing Method for Modular Multilevel Converters for HVdc Applications

Abstract: An analytical steady-state model of the modular multilevel converter (MMC) can be used for component sizing and assessment of the impact of different parameters on the MMC performance. Thus, this paper proposes an enhanced steady-state model for the MMC, which enables one to calculate the amplitudes of the harmonic components of MMC arm currents, submodule capacitor voltages, and arm voltages. In addition, the proposed model allows for the calculation of the amplitude and phase angle of the modulating signal, and it also presents a criterion for resonance of the arm currents. This is achieved by means of a polynomial function of the modulation index, and through checking the stability criteria established by the proposed model. The capability of formulating the modulating signal enables a more accurate calculation of the steady-state amplitudes of the variables, as compared to the previously published models. This paper also presents an accurate method of submodule capacitor sizing, based on the proposed steady-state model. The proposed method gives the exact value of the submodule capacitance (i.e., the capacitance that results in dc voltage fluctuations within a desired range) for a prespecified submodule capacitor voltage variation and a given circulating current amplitude. The stability criterion given by the proposed steady-state model, used for sizing the arm inductance, and the submodule capacitor voltage variation given by the proposed capacitor sizing method, used for sizing the submodule capacitor, allows for the determining of the operating limits of the MMC in terms of its parameters. Extensive simulation results are presented to demonstrate the efficacy of the proposed steady-state model and the capacitor sizing method. Further, the results obtained from the proposed capacitor sizing method are compared with experimental results from the literature.

Multipin Optimization Method for Placement of Decoupling Capacitors Using a Genetic Algorithm

Abstract: A genetic algorithm (GA)-based method is proposed for simultaneous optimization of decoupling capacitors assigned to multiple pins of a ball-grid array (BGA) package on a printed circuit board. A noise susceptibility parameter is introduced as the basis of a new set of GA fitness functions. Performance of several fitness functions is comparatively tested and discussed in case studies. The accuracy of the developed expressions is tested against full-wave electromagnetic simulation results. The proposed method is particularly useful for predicting the number and placement of decoupling capacitors under the BGA area of integrated circuit devices in early design stages and serves as a complement to rigorous algorithms that are used in the final phase of the design.

Development of a highly integrated 10 kV SiC MOSFET power module with a direct jet impingement cooling system

Abstract: High-density packaging of fast-switching power semiconductors typically requires low thermal resistance and low parasitic inductance. High-density packaging of high voltage semiconductors, such as 10kV SiC MOSFETs, has brought additional challenge. This work proposes a wire-bond-less, highly integrated planar SiC half-bridge module, with embedded decoupling capacitors and a high performance integrated thermal management system.

A Single-Phase Inverter/Rectifier Topology With Suppressed Double-Frequency Ripple

Abstract: This paper introduces a new bidirectional single-phase inverter topology. The proposed topology has three ports: a dc port, an ac port, and a ripple port. The ac and dc ports are bidirectional to support rectifier or inverter operation. A small inductor, which is of alternating current, exchanges power between different ports of the single-phase system. The proposed topology is capable of accomplishing voltage step-up or step-down, suppressing the ripple power, and performing inversion or rectification operation in one stage of power conversion. The proposed configuration offers an active decoupling function, which not only eliminates the double-frequency ripple power at the dc port but also achieves minimum capacitance requirements to minimize the size of the decoupling capacitor. This facilitates the use of a very small thin-film capacitor, which offers a much longer life-cycle and higher reliability compared with a bulky electrolytic capacitor. A control approach is also developed to regulate the dc-port and ac-port currents and manage the ripple power through proper distribution of power between each port. Moreover, a very small capacitor can be placed in parallel with the inductor to reinforce the proposed configuration with soft-switching operation, which enhances the overall efficiency and minimizes the voltage stress over the semiconductor devices. This converter is capable of accommodating an arbitrary number of dc or single-phase ac sources and/or loads configuring a multiple-input multiple-output inverter without introducing any additional passive elements or sacrificing the performance of the inverter. The primary focus of this paper is dc-to-ac conversion mode of operation, in spite of the fact that it can easily be configured to serve as a rectifier. Experimental and simulation results are presented to validate the operation of the proposed topology and its control strategy.

Design Considerations of Distributed and Centralized Switched-Capacitor Converters for Power Supply On-Chip

Abstract: On-chip power supply distribution faces the challenges of high and fast-changing load current, limited metal layers and decoupling capacitors, efficiency, and thermal issues. This paper mainly discusses system-level design considerations of both distributed and centralized fully integrated voltage regulators. In particular, a ring-shaped switched-capacitor dc-dc converter that has a unity-gain frequency a few times higher than its switching frequency is introduced with comprehensive considerations, and optimizing the number of time-interleaving phases (power cells) is detailed. Design issues such as on-chip power-rail routing parasitics, input capacitor and input ripple, and phase mismatch between power cells are addressed. Furthermore, a couple of possible extensions of the converter-ring architecture are proposed, which include power management of the active-matrix light-emitting diode array in a microdisplay system, cascading multiple nMOS-LDO regulators for granular power, and on-chip power converter grid with flipped-chip packaging.

Analysis of DC-Link Current Influence on Temperature Variation of Capacitor in a Wind Turbine Application

Abstract: Back-to-back converters for wind turbine systems feature capacitors in the dc-link to maintain a stable voltage and to decouple a generator from the electric grid The electrolytic capacitors are typically chosen for their advantages; a higher energy density and a higher capacitance at lower costs Long-term field experiences and recorded failure data revealed that the capacitors are one of the most frequent failure reasons for the wind turbine system The current profile of the capacitors is highly responsible for this degradation, since it determines the dissipated power of the capacitor This paper analyzes the actual current profile in the dc-link capacitor of a back-to-back converter for wind turbine application A power converter is also designed to generate sinusoidal current at arbitrary frequency and arbitrary dc bias voltage for testing purposes The experimental results confirm that the proposed power converter enables us to derive the correlation between the current frequency and the temperature variation of capacitor

Reinforcement Learning-Based Optimal on-Board Decoupling Capacitor Design Method

Abstract: In this paper, for the first time, we propose a reinforcement learning-based optimal on-board decoupling capacitor (decap) design method. The proposed method can provide optimal decap designs for a given on-board power distribution network (PDN). An optimal decap design refers to the optimized combination of decaps at proper positions to satisfy a required target impedance. Moreover, a minimum number of decaps should be assigned for optimal decap designs. The proposed method is applied to the test on-board PDN and successfully provided 37 optimal decap designs with 4 decaps assigned each. Self impedance of PDN with the provided design satisfied the required target impedance while minimizing the number of assigned decaps.

A Single Phase AC/DC/AC Converter With Unified Ripple Power Decoupling

Abstract: In single phase ac/dc/ac converters, the low frequency ripple powers exist both at the source and load sides Usually, large dc-link filter components are used to buffer the ripple powers, which increases volume and weight To overcome the drawback, this paper presents a single phase ac/dc/ac current source converter with unified ripple power decoupling The converter only consists of three bridge arms and a decoupling circuit The three bridge arms play the role of rectification and inversion with sharing a bridge arm And the decoupling circuit is in series with the dc-link energy storage unit to buffer the ripple powers The circuit configuration and operation principles are introduced first Then, a modulation strategy based on Cartesian space is developed to achieve sinusoidal input and output currents The control idea that the dc-link current is regulated by the decoupling circuit and the averaged decoupling capacitor voltage is maintained by the rectifier is adopted The ripple power buffer is automatically achieved Finally, the theoretical analysis is favorably verified by the simulations and experimental results

An Energy Efficient Charging Technique for Switched Capacitor Voltage Converters With Low-Duty Ratio

Abstract: Charging a capacitor array of a switched-capacitor (SC) dc-dc converter, supplying load circuits with a very short active period, can be pivotal to achieve high energy efficiency of its operation. This is because the capacitors may lose most of the stored energy during a long sleep period, and thus every sleep-to-active transition requires full recharging of the capacitors. In this brief, we present an energy efficient capacitor charging technique called split-capacitor charging, which charges a capacitor array in a step-wise fashion. Circuit simulations demonstrate that the proposed technique can reduce the energy wastage during sleep-to-active transition up to 66%. When tested on load circuits with a short active period, a voltage converter employing the proposed charging method shows up to 24% improvement in energy efficiency over conventional SC converters.

Micro-inverter based on single-ended primary-inductance converter topology with an active clamp power decoupling

Abstract: The reliability and lifespan of micro-inverters are two significant features of AC-module photovoltaic systems. One of the most effective methods to enhance the reliability and life duration of micro-inverters is achieved by substituting their electrolytic power decoupling capacitor with the film capacitors. In this study, a new DC/AC inverter based on an isolated single-ended primary-inductance converter with an active clamp power decoupling is introduced. The proposed converter has no electrolytic capacitor which results in long lifetime and high reliability. Moreover, the inverter has simple structure and low number of semiconductor switches which improve the efficiency and make it cost effective. The sufficient stepping up ability for output voltage without increasing turns ratio excessively, non-pulsating input current, and appropriate isolation make the proposed micro-inverter a proper choice for grid-connected applications. The converter operating modes are discussed and design considerations are presented. Finally, experimental results of the implemented prototype validate aforementioned features and performance of the proposed micro-inverter.

Power Decoupling for Single-Phase PV System Using $\acute{\mathrm{C}}$ uk Derived Microinverter

Abstract: This paper reports an elegant approach to address two major challenges of transformerless grid-connected microinverters, common-mode earth leakage current and double-frequency power pulsation across the photovoltaic (PV) terminal. The proposed solution uses an embedded decoupling capacitor in a doubly grounded boost–buck ( $\acute{\mathrm{C}}$ uk) derived topology. An intelligent switching scheme ensures that a large swing of the decoupling capacitor voltage is easily accommodated. Thus, film capacitors can be used instead of electrolytic capacitors, which helps increase equipment lifetime. Details of circuit operation are provided along with dynamic modeling and controller design for close-loop operation. Simulation and experimental results are presented for performance validation of the microinverter.

Investigation of thermal effects and lifetime estimation of electrolytic double layer capacitors during repeated charge and discharge cycles in dedicated application

Abstract: The article is firstly focused on thermal analysis of electrolytic double layer capacitor (EDLC) operated at repeated cycles of charging and discharging. This process is mostly applied at switched mode power supplies (SMPS), where electrolytic capacitor within given period of operation acts as energy storage element (discharge period). Charging and discharging process of EDLC may cause additional heating, which consequently influences capacitor’s lifetime. This parameter (lifetime) is nowadays very important parameter of EDLC, because operational life of the most of complex power electronic systems is directly influenced by its most critical components, i.e., by electrolytic capacitors. In this paper, the theory necessary for capacitor analysis and analysis of heat transfer is presented. The particular aluminum electrolytic capacitor Nichicon is examined in the paper. The implementation of real model into COMSOL Multiphysics and consequent simulation settings are being described too. Based on the main parameters of target application, the simulation analysis is processed. These results are consequently verified by experimental measurements on a given sample of EDLC. Deviations between measured and simulated data are identified, and optimization steps for better accuracy are also given. Finally, the factors influencing the lifetime of electrolytic capacitors together with calculation of capacitor’s lifetime in power application are described. During lifetime estimation, heat transfer simulation modeling of capacitor is utilized. Presented approach offers acceleration of necessary variables identification, which are hardly to be identified with the use of measurements, e.g., capacitor’s core temperature. Thus, more accurate results regarding lifetime estimation can be achieved.

Efficient Decoupling Capacitor Placement Based on Driving Point Impedance

Abstract: With rapidly increasing switching speeds and surge current requirements, placement of local decoupling capacitors is becoming critically important in high-speed low-power designs. In this paper, utilizing the driving-point impedance (viewed from the device pin) as a metric, a new method is presented for the placement of decoupling capacitors in parallel-plate power ground pairs of high-speed circuits. In the proposed approach, instead of using the traditional trial-and-error method to identify an appropriate placement distance, the process is formulated in the form of a transcendental function. The resulting function is solved using Newton–Raphson (N-R) iterations to give a direct solution for the distance. Also, an analytical representation based on Hankel functions for the driving point impedance and its derivatives is developed to speed up the N-R iterations. The proposed method is validated by comparing the results with the full-wave electromagnetic simulations.

PCB PDN Prelayout Library for Top-Layer Inductance and the Equivalent Model for Decoupling Capacitors

Abstract: The power distribution network (PDN) of a high-speed printed circuit board requires a high-performance power supply. The total equivalent inductance above the top ground plane is an important part of PDN design and is regarded as L above. In this paper, an inductance library for different structures of capacitor connections and capacitor sizes has been built, which is essential for PDN design. computer simulation technology (CST) and partial element equivalent circuit method are applied to obtain the shorted pattern design curves at various design data. The shorted pattern design curve means the total equivalent inductance varies with the distance between pad and ground plane. In addition, an approximate shorted model is established for a decoupling capacitor-mounted model, which will be convenient for us to get the inductance of L above. In this paper, the design curve provides an intuitive guideline in designing PDN and facilitates the industry to choose what they want with consideration of the inductance, space, via numbers, etc.

Performance evaluation of single-phase transfomer-less PV inverter topologies

Abstract: Double line frequency power decoupling with reduced capacitance and mitigation of leakage current are two of the major challenges of any grid-connected single phase photovoltaic (PV) inverter. This paper compares the performances of different topologies for single phase transformerless PV application in terms of the power decoupling capacitor requirement, the current ripple and total harmonic distortion (THD), efficiency performance, and leakage current. The topologies considered include a doubly grounded T-type dynamic dc-link (DDCL) inverter, a half-bridge voltage swing (HBVS) inverter, and conventional full-bridge (FB) inverter with three different modulation schemes (bipolar, hybrid, and unipolar). The leakage current arising from both parasitic capacitances of the PV module and the heat sink is considered in the present study which is essential for design of the electromagnetic interference (EMI) filters. The analysis are supported by experimental results from SiC-based 1 kW hardware prototypes operating at 120 V ac nominal output at a switching frequency of 100 kHz for each of the topology.

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Abstract: In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

31 DBM Sensitivity High Efficiency Rectifier For Energy Scavenging

Abstract: RF energy scavenging is capable in converting RF signals into electricity and has become a promising solution to power energy-constrained wireless networks. However, it has low power conversion efficiency especially when the harvested RF power is small. For this reason, we propose an enhanced differential-drive rectifier to improve the efficiency and the sensitivity of rectifier for energy scavenging applications. The proposed rectifier achieves dynamically controlled threshold voltage and reduces leakage current in the transistors through DTMOS transistor in differential-drive topology. The voltage boosting circuit further increases the sensitivity through step up the input signal before the signal enters the rectifier. The decoupling capacitor shunts the noise of the input signal before the signal is injected into the cross-connected gate reducing the voltage drop and maintaining the PCE of the rectifier. The rectifier is designed based on the 0.18 µm Silterra CMOS process technology. Effects of decoupling capacitors, voltage boosting circuit and output load on PCE of the rectifier have been evaluated. Technology scaling and parasitic effects to the rectifier have also been presented. Performance of N-stages proposed rectifier has been compared with the conventional BTMOS rectifier. The proposed method achieves the highest sensitivity of −31 dBm for 1, 3 and 5 stages rectifiers without the need of off-chip load capacitor.