Showing papers on "Decoupling capacitor published in 2020"

Estimation, Minimization, and Validation of Commutation Loop Inductance for a 135-kW SiC EV Traction Inverter

Abstract: With growing interests in low-inductance silicon carbide (SiC)-based power module packaging, it is vital to focus on system-level design aspects to facilitate easy integration of the modules and reap system-level benefits. To effectively utilize the low-inductance modules, busbar and interconnects should also be designed with low stray inductances. A holistic investigation of the flux path and flux cancellations in the module-busbar assembly, which can be treated as differentially coupled series inductors, is thus mandatory for a system-level design. This article presents a busbar design, which can be adopted to effectively integrate the CREE’s low-inductance 1.2-/1.7-kV SiC power modules. This article also proposes a novel measurement technique to measure the inductance of the module-busbar assembly as a whole rather than deducing it from individual components. The inductance of the overall commutation loop of the inverter that encompasses the SiC power module, interconnects, and printed circuit board (PCB) busbar has been estimated using finite-element analysis (FEA). Insights gained from FEA provided the guidelines to decide the placement of the decoupling capacitors in the busbar to minimize the overall commutation loop inductance from 12.8 to 7.4 nH, which resulted in a significant reduction in the device voltage overshoot. The simulation results have been validated through measurements using an impedance analyzer (ZA) with less than 5% difference between the extracted loop inductance from FEA and measurements. The busbar design study and the measurement technique discussed in this article can be easily extended to other power module packages. Finally, the 135-kW inverter has been compared to a similar high-power inverter utilizing a laminated busbar to highlight the performance of the former.

Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D/3-D ICs

Abstract: In this article, we first propose a deep reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for silicon interposer-based 2.5-D/3-D integrated circuits (ICs). The proposed method provides an optimal decap design that satisfies target impedance with a minimum area. Using deep RL algorithms based on reward feedback mechanisms, an optimal decap design guideline can be derived. For verification, the proposed method was applied to test power distribution networks (PDNs) and self-PDN impedance was compared with full search simulation results. We successfully verified by the full search simulation that the proposed method provides one of the solution sets. Conventional approaches are based on complex analytical models from power integrity (PI) domain expertise. However, the proposed method requires only specifications of the PDN structure and decap, along with a simple reward model, achieving fast and accurate data-driven results. Computing time of the proposed method was a few minutes, significantly reduced than that of the full search simulation, which took more than a month. Furthermore, the proposed deep RL method covered up to $10^{17}$ – $10^{18}$ cases, an approximately $10^{12}$ – $10^{13}$ order increase compared to the previous RL-based methods that did not utilize deep-learning techniques.

A Chip-First Microwave Package Using Multimaterial Aerosol Jet Printing

Abstract: We show in this article two fully additively manufactured microwave packages with integrated active and passive components. Packages were constructed using a chip-first approach where package substrates (dielectrics) and interconnects (conductors) are built up around power amplifier bare die attached to carriers. Bypass capacitor dielectrics were printed using multimaterial aerosol jet printing, where aerosols of barium titanate and polyimide inks are mixed in place to fabricate a high dielectric constant polymer matrix nanocomposite film. The material properties of the film are characterized using three printed capacitors. We present S-parameter measurements to characterize small-signal performance, as well as load–pull measurements at the saturated output power. Finally, we demonstrate package performance after power cycling and temperature cycling to show the effect of aging on the part and the robustness of this packaging strategy. We measured a maximum packaged gain of 21.7 dB and a saturated output power of 21.9 dBm for a commercial-off-the-shelf (COTS) medium power amplifier specified to have a gain of 22 dB and a saturated output power of 22 dBm. The printed package-level performance is compared with the published bare die performance and a measured COTS packaged amplifier.

Modulation Method and Control Strategy for Full-Bridge-Based Swiss Rectifier to Achieve ZVS Operation and Suppress Low-Order Harmonics of Injected Current

Abstract: The Swiss-type rectifier (SR) uses a three-phase unfolder circuit to convert the ac voltage into two time-varying positive voltages. The power factor correction of ac sides and the stable dc voltage output can be realized by using two dc–dc topologies without any bulky decoupling capacitors. By applying the phase-shifted full-bridge topology into the dc structure, both the soft-switching and the high-frequency electrical isolation can be achieved. However, the power coupling between two full bridges using the traditional modulation method will affect the zero-voltage switching (ZVS) condition of lagging legs. Then, the duty cycle loss caused by the transformer leakage inductance will affect the input and output performance. Therefore, a new method using the up-counting mode modulation is proposed to implement the ZVS for both the lagging switches. Then, the relationship between the duty cycle loss and the extra 6 N ± 1 harmonics added into the input current is theoretically analyzed. Hence, to suppress the low-order harmonics, a novel compensation strategy is proposed. The proposed modulation method and control strategy have been successfully verified by the experiments. 95% efficiency under half-rated power and 3% input current total harmonic distortion (THD) under rated power have been achieved under a 10-kW 380 Vac input/400 Vdc output prototype with 90-kHz switching frequency.

A High-Performance Embedded SiC Power Module Based on a DBC-Stacked Hybrid Packaging Structure

Abstract: Silicon carbide (SiC) devices have the advantage of high switching speed. However, the switching speed is limited by the high parasitic inductance which could cause high voltage overshoot, parasitic turn-on, oscillation, and electromagnetic interference (EMI) issues. Thus, the parasitic inductance of the SiC power module has to be reduced for better performance. This paper proposed an integrated half-bridge (HB) power module based on a direct bonding copper (DBC)-stacked hybrid packaging structure. This packaging structure utilizes two DBC substrates to stack together, which form a 3-D power commutation loop. The SiC chips are embedded on the top of the bottom DBC substrate to reduce the thermal resistance. Based on an optimized mutual inductance cancellation design, the proposed DBC-stacked hybrid packaging structure has only 1.8-nH commutation power loop inductance for a 1200-V, 120-A HB power module. Moreover, the geometrical parameters of the laminated power terminal have been analyzed and optimized for the symmetrical current sharing in the multichip paralleled power module. A compact 1200-V, 120-A full SiC HB power module with integrated decoupling capacitors has been fabricated and the dc-link capacitor board, gate drivers can be integrated on the power module compactly. Finally, the static and dynamic characteristics of the proposed module have been tested. The results of double pulse test (DPT) under zero external driver resistor indicate that the voltage overshoot of the proposed module is reduced by approximately 55% compared to the commercial power module, and the total switching energy is only 43% of the commercial module. Moreover, the loss of the 5.5-kW single-phase inverter based on the proposed module is reduced by 28.3% compared with the inverter based on the commercial module under 120-kHz switching frequency.

A Double-Sided Cooling 650V/30A GaN Power Module with Low Parasitic Inductance

Abstract: This paper presents a compact double-sided cooling Gallium Nitride (GaN) power module with low parasitic parameters. The GaN bare dies are sandwiched between two ceramic substrates with high thermal conductivity to achieve efficient double-sided cooling capability. Through careful design and layout optimization, the bus decoupling capacitors and core drive components are successfully integrated into the module to reduce critical parasitic parameters. The thermal and parasitic characteristics of the module are analyzed and optimized. Finally, a double-pulse-test platform is built based on the presented 650V/30A GaN power module. The results show that the power loop inductance is reduced to 0.95 nH and the gate loop inductance is reduced to about 2nH. The dv/dt of the drain-source voltage can be as high as 150V/ns, while the overshoot is only 10%.

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Abstract: This article proposes an LDO with fast response to load transients that can handle any practical capacitive loads. These features are mainly due to a novel frequency compensation circuit tailored for its error amplifier, which is based on an improved version of the popular common gate amplifier. A simple yet effective approach to the small-signal analysis of LDO with multiple feedback loops is employed to analyse intuitively the LDO and derive key design constraints. Simulation and measurement results performed on a test chip implemented in standard 130nm CMOS process validated the proposed LDO. It requires only $0.7\mu \text{A}$ quiescent current but exhibits an excellent response to load transients: when the load current jumps from 0A to 100mA in $1\mu \text{s}$ the output voltage presents an undershoot of 76mV and an overshoot of 198mV, without decoupling capacitors. It compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifiers. A figure-of-merit that considers the quiescent current, the maximum load current and capacitance, as well as the output voltage deviation, yielded a value for our LDO 39.8 times better than for the nearer competitor that employs common gate amplifier and 6 times better than the one employing a different error amplifier. When considering edge time and process scaling the performance of the proposed LDO is 4.8, respectively 4.5, times better than the second best in both comparisons.

Genetic Algorithm PDN Optimization based on Minimum Number of Decoupling Capacitors Applied to Arbitrary Target Impedance

Abstract: The current demand in Power Distribution Network (PDN) design is characterized by the accurate placement of decoupling capacitors and the minimization of their number aimed at cost saving. The paper proposes an optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution. This allows the designer to identify the minimum number of decaps whenever the input impedance satisfies the target impedance requirements. The algorithm is based on the Genetic Algorithm accordingly adapted for the specific application of PDN design. It may involve the evaluation of the input impedance at multiple locations, representing either multiple ICs, as well as multiple power input areas/pins of the same IC. The validation of the developed optimization algorithm is carried out by applying it to a manufactured PCB and by employing typical (low inductance) decaps for PDN design. The optimization process led to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location. An accurate experimental test further validates the optimized PDN.

A K -Band High Interference-Rejection GaAs Low-Noise Amplifier Using Multizero Control Method for Satellite Communication

Abstract: This letter presents a 17.5–22.5-GHz low-noise amplifier (LNA) with the high out-of-band rejection in the range of 27.5–32.5 GHz and 4–10 GHz by using 90-nm GaAs p-HEMT technology. The multizero control method is proposed to produce multiple zeros for generating the high out-of-band rejection and expanding the rejection bandwidth. The multizero control is realized by bypass capacitor notch filters at the drain of transistors and shunt capacitor notch filters at the interstage matching circuits. By using this approach, the high rejection can be achieved at unwanted frequencies without additional devices. Also, the multizero control is mainly implemented in the transistor’s bypass branch, which can achieve the low noise figure (NF) well within the whole operating band. The cost and integration of the front end can also be improved. The measured maximum gain is 23.9 dB at 19 GHz, and the 3-dB bandwidth is 17.5–22.5 GHz. The good interference rejection of the proposed LNA is from 57 to 73 dB and 61 to 72 dB in the range of 4–10 GHz and 27.5–32.5 GHz, respectively. The measured NF is 1.1–1.3 dB. The LNA area is 2 mm $\times1.3$ mm including pads.

An Enhanced Deep Reinforcement Learning Algorithm for Decoupling Capacitor Selection in Power Distribution Network Design

Abstract: The selection of decoupling capacitors (decap) is a critical but tedious process in power distribution network (PDN) design. In this paper, an improved decap-selection algorithm based on deep reinforcement learning (DRL), which seeks the minimum number of decaps through a self-exploration training to satisfy a given target impedance, is presented. Compared with the previous relevant work: the calculation speed of PDN impedance is significantly increased by adopting an impedance matrix reduction method; also, the enhanced algorithm performs a better convergence by utilizing the techniques of double Q-learning and prioritized experience replay; furthermore, a well-designed reward is proposed to facilitate long-term convergence when more decaps are required. The proposed algorithm demonstrates the feasibility of achieving decent performance using DRL with pre-trained knowledge for more complicated engineering tasks in the future.

Power Delivery Exploration Methodology Based on Constrained Optimization

Abstract: The conventional power network design process requires iterative modifications to the existing power network to eliminate hot spots and to converge to target impedance parameters. At later stages in the IC design process, this procedure may require significant time and human resources due to the limited flexibility to accommodate necessary changes. Power delivery exploration during early stages of the design process may bring considerable savings to the system development effort. The number of iterations may be greatly reduced by choosing the initial parameters sufficiently close to the optimum. This paper presents a power delivery exploration framework based on constrained global optimization. The power network parameters are estimated at early stages of the development process, while considering both electrical and nonelectrical factors, such as area and cost. A Laplace transform-based circuit simulator is described that is well suited for optimization purposes due to the high computational efficiency when a large number of iterations is required. The proposed framework has been applied to the distribution of voltage domains in a large scale complex integrated system, while minimizing the cost of the decoupling capacitor placement. The optimal number of voltage rails are determined, demonstrating an approximately 40% lower on-chip area than alternative solutions.

Modeling and Experimental Assessment of the EMI Characteristics of Switching Converters With Power Semiconductor Filters

Abstract: An input filtering technology named “power semiconductor filter (PSF)” has been proposed recently. Its operating principle is based on using a series pass device (SPD) to profile the wave shape and magnitude of the input current of converters. The voltage across the SPD is regulated around the “knee point” of the current–voltage characteristic of the SPD to minimize the power dissipation of the SPD. This paper reports the conducted electromagnetic interference (EMI) performance of the converters with the PSF. To suppress differential-mode (DM) EMI, a fast current regulation circuit is proposed to tightly regulate the current through the SPD. To suppress common-mode (CM) EMI, a single CM noise bypass capacitor is proposed. Detailed mathematical models for describing the frequency response of the SPD and main components in the driving network are formulated. A set of selection guidelines for the components will be given. The derived models will be validated by comparing the theoretical prediction with the measurement results of a 100 W, 90–264 Vac LED driver using a buck–boost converter. Results reveal that the PSF reduces the DM noise level by 47.47 dBμV. The CM noise level is reduced by 21.4 dBμV with the bypass capacitor. An integrated circuit for the controller is illustrated to demonstrate the feasibility of reducing the form factor of the filtering section.

Effective PCB Decoupling Optimization by Combining an Iterative Genetic Algorithm and Machine Learning

Abstract: An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm (GA) and Artificial Neural Network (ANN). The ANN is first trained by an appropriate set of results obtained by a commercial simulator. Once the ANN is ready, it is used within an iterative GA process to place a minimum number of decoupling capacitors for minimizing the differences between the input impedance at one or more location, and the required target impedance. The combined GA–ANN process is shown to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators. With the new approach the accuracy of the results remains at the same level, but the computational time is reduced by at least 30 times. Two test cases have been considered for validating the proposed approach, with the second one also being compared by experimental measurements.

Single-Phase Voltage Source Inverter With Voltage Boosting and Power Decoupling Capabilities

Abstract: This article proposes a single-phase bridge inverter with both voltage boosting and power decoupling capabilities. The proposed inverter topology diverts the second-order ripple power into a small film capacitor instead of using a bulky electrolytic capacitor at the dc side, thus eliminating the large electrolytic capacitor that has a short lifetime. The voltage across the decoupling capacitor is controlled as a dc-biased sine wave to cancel out the second-order ripple power originated from the single-phase grid power, and the dc offset in the decoupling capacitor is used to boost the dc-link voltage, as opposed to being under-utilized in previous dc voltage-reference power decoupling techniques. The proposed topology also maintains the advantages of the traditional bridge inverters with the unipolar sinusoidal pulsewidth modulation technique. Moreover, the output filter and power decoupling control method are designed for the proposed inverter. Finally, the simulation and experimental results verify the feasibility of the proposed topology and control algorithm, which show successful voltage boosting and power decoupling functions.

An Integrated Energy Storage System With Voltage Balancing Based on Switched-Capacitor Reutilization Techniques

Abstract: On account of complementary control, reduced size, and energy saving, the switched-capacitor (SC) based equalizer becomes promising for the energy management of energy storage system. Traditionally, the number of the bypass capacitor in the SC based equalizer equals to the number of the battery module in series or parallel connections. The amount of bypass capacitors is enormous, thus costly and bulky for electric vehicles (EVs). In this paper, the integrated energy storage is proposed to reduce cost and save space, meanwhile, the equalizations between the batteries and the ultracapacitors (UCs) are achieved by the reutilization of SC network. UCs not only perform as energy storage units, but also work as energy exchange units. Thus, the number of balanced elements can be reduced significantly. The operational principles of the storage system and the analyses of the balancing process are examined in detail. The system simulation is performed for functionality evaluations. Meanwhile, an experimental prototype is also implemented for six cells to demonstrate the balancing process. The accordance of experiment and simulation can further testify the feasibility and effectiveness.

Power Integrity Performance Gain of a Novel Integrated Stack Capacitor (ISC) Solution for High-end Computing Applications

Abstract: An integrated stack capacitor (ISC) solution, which can effectively suppress power noise in high frequency bands, is introduced. The basic structure of the ISC is a vertical cylinder array consisting of many capacitive vias. The proposed ISC shows high capacitance density compared to the existing silicon capacitors. In this study, the power integrity (PI) performance gain of the proposed ISC solution was analyzed by applying it to the advanced package platforms such as 2.5D silicon interposer, fanout (FO) package, RDL interposer, and substrate based chiplet. Based on 3D wafer on wafer (WoW) technology, ISC is a not only 2.5D silicon interposer for high performance computing (HPC) and server that operates with high power, but also a novel silicon capacitor solution that can be applied to substrate and fanout packages for mobile and automotive.

Decoupling Capacitor Placement Optimization With Lagrange Multiplier Method

Abstract: This paper proposes a decoupling capacitor placement optimization method based on the cavity model and Lagrange multiplier. The variable conditions associating with coordinates (x,y) of input impedance expression based on the cavity model are combined with the Lagrange multiplier method. The decoupling capacitor optimum placement within a defined area of the board can be found through the proposed analytical method. The example of finding an optimum location of the decoupling capacitor within a defined area of the power delivery network is exposed, the results are compared to the brute-force method to prove the effectiveness of the proposed method.

Impedance Network Impact on the Controller Design of the QZSI for PV Applications

Abstract: Due to its buck-boost capability with a continuous input current, the quasi-Z-source inverter (qZSI) is increasingly used for renewable energy, e.g., photovoltaic (PV) systems. The quasi-Z-source network (qZSn) enables an additional state, i.e., shoot-through (ST) state, which extends the entire system reliability to some extent. Unlike the conventional two-stage inverter with a large dc-link decoupling capacitor, the qZSn is strongly coupled with the ac part, making the system dynamically interactive. However, the controller for the ac part of the qZSI is generally designed like that for the conventional voltage source inverter (VSI), which may become ineffective. This paper thus presents the small-signal modeling of the three-phase qZSI and the effect of the impedance network on the control of the qZSI is then analyzed. The resonance due to the load and input changes has been analyzed and then used in the ac controller design. Both simulation and experimental tests are presented to verify the theoretical analysis and designed controller.

Policy Gradient Reinforcement Learning-based Optimal Decoupling Capacitor Design Method for 2.5-D/3-D ICs using Transformer Network

Abstract: In this paper, we first propose a policy gradient reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for 2.5-D/3-D integrated circuits (ICs) using a transformer network. The proposed method can provide an optimal decap design that meets target impedance. Unlike previous value-based RL methods with simple value approximators such as multi-layer perceptron (MLP) and convolutional neural network (CNN), the proposed method directly parameterizes policy using an attention-based transformer network model. The model is trained through the policy gradient algorithm so that it can achieve larger action space, i.e. search space. For verification, we applied the proposed method to a test hierarchical power distribution network (PDN). We compared convergence results depending on the action space with the previous value-based RL method. As a result, it is validated that the proposed method can cover ×4 times larger action space than that of the previous work.

Low Power SOC Based on High Density MIM Capacitor for beyond Moore Era by Robust Power Integrity Achievement

Abstract: In this paper, the methods for improving the PI (Power Integrity) of low power SOC (System-On-Chip) are discussed. In order to confirm the PI improvement effect by using MIM (Metal-Insulator-Metal), system-level PDN impedance and voltage drop was analyzed for cores with one LICC (Low Inductance Ceramic Capacitor) embedded in the package. Compared to the case where no decoupling capacitor was applied, the PI characteristics were improved when the LICC (Low Inductance Ceramic Capacitor) was inserted in the package substrate, and more dramatic improvement can be achieved by using MIM. When the embedded decoupling capacitor and the MIM capacitor corresponding to the core area are used at the same time, the system-level PDN impedance is reduced by less than half compared with the case where only the embedded LICC is used. Also, it was confirmed by simulation and measurement that voltage drop and voltage ripple can be reduced by implementing MIM. In particular, MIM has been analyzed to be more effective at high frequencies than conventional ceramic capacitors, making it a suitable PI improvement solution for the beyond Moore era.

Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel’s 10+ Process

Abstract: We present a high density MIM decoupling capacitor that enables improved microprocessor performance by providing robust on-chip power supply droop reduction The MIM dielectric is fabricated using ALD-deposited HfO 2 -Al 2 O 3 and HfO 2 -ZrO 2 high-k dielectrics with PVD TiN electrodes We achieve single MIM-cap densities of 37 fF/μm2 and 52 fF/μm2 that meet reliability requirement for both 198 V and 126 V use conditions The reliability of the HfO 2 -ZrO 2 capacitor shows minimal voltage polarity dependence, which enables the use of multi-plate MIM-caps to increase capacitance density We achieved a capacitance density of 141 fF/μm2 with a four-plate configuration, representing a 35× improvement over the reported capacitance density on Intel’s 14 nm process In addition, the stack meets environmental stress tests This MIM- cap improves the on-chip power delivery network, leading to an increase in maximum frequency of microprocessors and is now shipping in volume

Noise Suppression and Precise Phase Control of a Commercial S-Band Magnetron

Abstract: We demonstrate noise suppression and precise phase control of a commercial 2.45GHz magnetron aiming for wireless power transfer application. The impurity of the microwave spectrum was confirmed to be due to the switching frequency of 76kHz in the power supply. With the decoupling capacitor installed to the output of the high-voltage power-supply driving the magnetron, the spectral purity of the magnetron was significantly enhanced. And we achieved extreme precision in phase-control (peak-to-peak 0.3°) for the high-power (1 kW) microwave magnetron by applying the phase locking loop to the noise-suppressed magnetron system.

Deep Trench Capacitors in Silicon Interconnect Fabric

Abstract: Silicon interconnect fabric (Si-IF) technology is a PCB replacement, fine pitch heterogeneous integration platform that enables high package density by supporting dielet assembly at small inter-dielet spacing. Electrical analysis of a back-side power delivery architecture for Si-IF is performed in this paper. To extend the frequency range of operation of the power delivery network (PDN), decoupling capacitors need to be used, which are implemented in Si-IF as deep trench capacitors (DTCAPs). DTCAPs with high specific cap density greater than $100\frac{{fF}}{{\mu {m^2}}}$, low effective series resistance (≤ 1 mΩ), break down voltage greater than typical operating voltage, and process flow compatible for integration in Si-IF is targeted. Fabrication and experimental characterization of DTCAPs in Si-IF is currently a work in progress. Some early fabrication results are presented.

Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop

Abstract: A delay-locked loop (DLL), which is widely used to compensate for the timing of high-speed data communications, was designed and fabricated in a 180 nm CMOS process. The DLL integrated circuit was assembled on a simplified motherboard and the module structures of a laptop computer and was tested under electrostatic discharge (ESD) events. The input and output voltages of the DLL under ESD-induced noises were measured, and the average values of peak-to-peak jitter and jitter durations of the DLL clock were obtained from repeated measurements. The effects of the voltage-drain-drain (VDD) decoupling capacitors and a bias decoupling capacitor were investigated. SPICE simulations were conducted using the measured input voltages and were compared with the measured results. The root causes of the ESD-induced DLL jitter were identified by analyzing the waveforms from the SPICE simulations. Employing VDD decoupling capacitors and maintaining the amount of delay control parameters for delay cells in the DLL were crucial in reducing jitter. The measured ESD-induced VDD noises were also validated and analyzed using impedance parameter measurements.

Decoupling capacitor power ground via layout analysis for multi-layered PCB PDNs

Abstract: A modeling methodology to calculate the decoupling capacitor interconnect inductance in a multi-layer PCB is proposed herein. The methodology is based on the resonant cavity model of parallel planes. The self-inductance and mutual inductance are extracted to understand the via configuration influence on the effectiveness of decoupling capacitors. A special layout of decoupling capacitor is proposed to increase the effectiveness of the decoupling capacitors by taking maximum advantage of the mutual inductance between interconnect vias with two decoupling capacitors placed in a pair, and two pairs of power and ground vias placed in alternating directions as close as possible. The number of decoupling capacitors needed can be reduced dramatically. Three PCB PDN designs are used to present the effectiveness of doublet layout in different design scenarios. Similar analysis is extended to 3-terminal decoupling capacitor layout design. The decoupling capacitor interconnect inductance of the five via layouts for 3-terminal capacitors is analyzed. The number of decoupling capacitors needed for a commercial product using the doublet layout and 3-terminal capacitor layout is compared to the design with an alternating decoupling capacitor layout to reflect the impact of the decap layout design on the PCB PDN performance.

A Non-Random Exploration based Method for the optimization of Capacitors in Power Delivery Networks

Abstract: This paper proposes a non-random exploration based method to optimize the response of power delivery network (PDN) using the minimum number of capacitors. Unlike previous optimization methods which are based on either full search or random exploration (machine learning etc), the present method requires few simulations to converge to the minimum decoupling capacitor solution. The results show that the proposed method is more robust based on comparisons.

Decoupling Capacitor Layout Design Guidelines for Acoustic Noise Consideration in Power Distribution Network

Abstract: Acoustic noise induced by multilayer ceramic capacitors (MLCCs) in power distribution network (PDN) is a critical issue regarding product user experience. In this work, design guidelines for decoupling capacitor selection, layout geometries are proposed targeting the acoustic noise, through analysis of the acoustic noise generation mechanism in printed circuit board (PCB). A test board is designed to validate the proposed design guidelines. With sound pressure level measurement of the test vehicle, the effectiveness of the proposed design guidelines is confirmed. In general, the decoupling capacitor layout design guidelines for acoustic noise consideration are consistent with the requirements for PDN to achieve high electrical performance.

3D IC decoupling capacitor structure and method for manufacturing the same

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

On the Effective Range of Decoupling Capacitors Including Mutual Coupling

Abstract: A method is proposed to calculate the effectiveness of a decoupling capacitor in the presence of other capacitors. The previously developed scalar expressions for calculating the effective radius of a capacitor in isolation are extended to matrix relations which account for mutual coupling. In the same vein, the scalar operations are substituted by their matrix counterparts including the calculation of derivatives using matrix calculus techniques which are required for the iterative solution of the problem. The proposed method is tested on a sample case and the results are observed to compare favorably against those from a numerical electromagnetic (EM) simulator.

Circuit Models for the Inductance of Eight-Terminal Decoupling Capacitors

Abstract: The series inductance associated with decoupling capacitors can contribute significantly to the impedance of the power distribution network. The eight-terminal capacitors considered in this article have a lower self-inductance than two-terminal capacitors and are commonly used in IC packages. Manufacturers typically specify the inductance of the capacitor using some type of equivalent series inductance (ESL), but this ESL may not accurately predict the inductance seen during use because it does not account for the coupling between the capacitor and nearby structures like the return plane. To adequately determine the inductance associated with an eight-terminal capacitor, models of typical eight-terminal capacitors were developed in Dassault Systemes CST Studio Suite. The partial element equivalent circuit (PEEC) method was used to construct simple models that can be simulated in SPICE. PEEC provides analytic insight into the source of inductance. Modeling the electrode stack as a solid block rather than a multilayer structure was shown to only change the computed inductance by 3% (~1 pH) and to substantially reduce the compute time. CST and PEEC models agreed within 9% (~3 pH), demonstrating the adequacy of the simpler PEEC models. Studies of the impact of the design parameters demonstrate that the distance between the capacitor and the reference plane has the greatest influence on inductance and that the placement of vias within the pads is important.