Showing papers on "Decoupling capacitor published in 2021"

Busbar Design and Optimization for Voltage Overshoot Mitigation of a Silicon Carbide High-Power Three-Phase T-Type Inverter

Abstract: The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Finally, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies.

Partial Power Processing for Power Decoupling Network in Three-Phase Three-Leg Four-Wire Three-Level T-Type Inverter with Reduced Split DC-Bus Capacitance

Abstract: The three-phase three-leg four-wire (3P3L4W) three-level (3L) inverter demands large split dc-bus capacitors for limiting the voltage ripple resulting from the neutral current, which mainly pulsates at the fundamental output frequency, and the midpoint current, which mainly pulsates at triple the output frequency. This paper embeds a power decoupling network (PDN) in the basic 3P3L4W 3L inverter for reducing the split dc-bus capacitance. To curb excessive power losses, partial power processing is proposed to make the PDN partially bypass the neutral current and the midpoint current, such that the split dc-bus capacitance could be reduced at the expense of affordable power losses. Finally, a 10 kVA PDN embedded 3P3L4W 3L T-type inverter is built and tested in the lab, and experimental results are presented to verify the feasibility of the proposed work.

A 93.7% Efficient 400A 48V-1V Merged-Two-Stage Hybrid Switched-Capacitor Converter with 24V Virtual Intermediate Bus and Coupled Inductors

Abstract: This paper presents a 93.7% efficient 400 A 48 V-1 V merged-two-stage hybrid switched-capacitor converter with 24 V virtual intermediate bus and coupled inductors. The first stage of the converter is a 2:1 interleaved charge pump which converts the 48 V input voltage to a virtual intermediate bus at 24 V. The second stage contains multiple paralleled 24:1 four-phase series capacitor buck modules with coupled inductors which have an equivalent voltage conversion ratio of 6:1. The two stages are linked by a 24 V virtual intermediate bus with small decoupling capacitor and voltage ripple. The hybrid switched capacitor architecture enables high efficiency, high power density, and high control bandwidth for ultra-high-current point-of-load applications. The effectiveness of the topology is verified by a 48 V-1 V 400 A prototype with a peak efficiency of 93.7% at 120 A and a full load efficiency of 88.7% at 400 A. The power density of the prototype is 342 W/in3. Compared to a decoupled-two-stage design, the merged-two-stage design reduces the passive component size at the cost of slightly reduced efficiency.

SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping

Abstract: The board-level power network design process is governed by system-level parameters such as the number of layers and the ball grid array (BGA) pattern. These parameters influence the characteristics of the resulting system, such as power, speed, and cost. Evaluating the impact of these parameters is, however, challenging. To estimate the reduction in impedance if, for example, additional BGA balls are dedicated to the power delivery system, adjustments to the board layout and an additional impedance extraction process are required. These processes are poorly automated, requiring significant time and labor. Automating power network exploration and prototyping can greatly enhance the power delivery design process by increasing the number of possible design options. With power network exploration and prototyping, the effects of the system parameters on the electrical characteristics can be better understood, providing valuable insight into the early design stages. SPROUT - an automated algorithm for prototyping printed circuit board (PCB) power networks - is presented here. This tool includes the first fully automated algorithm for board-level power network layout synthesis. Two board-level industrial power networks are synthesized using SPROUT where a ball grid array is connected with a power management IC and decoupling capacitors across four voltage domains. The impedance of the resulting layouts is in good agreement with manual PCB layouts while requiring 95% less design time.

Measurement and Analysis of Electromagnetic Information Leakage From Printed Circuit Board Power Delivery Network of Cryptographic Devices

Abstract: This article presents a novel measurement and analysis of electromagnetic (EM) information leakage from printed circuit board (PCB) power delivery network (PDN) of cryptographic devices. We propose an accurate EM information leakage analysis method based on a correlation electromagnetic analysis (CEMA) considering advanced encryption standard (AES) operation cycles and clock frequency. We measure field distribution on the PCB level AES core PDN and conduct the proposed analysis method to derive the information leakage maps. For the first time, we verified that the EM information leakage depends on the intensity of dominant field distribution on the PCB PDN using the proposed method. We validated that the whole secret key information can be extracted from locations in the PCB PDN distant from the cryptographic integrated circuit where a specific field is dominant due to the physical structure of the PCB PDN. Based on the measurement and analysis results, we discuss an efficient EM information leakage evaluation method based on the dominant field radiation. We evaluate the EM information leakage from the decoupling capacitor in the backside of the PCB. Finally, we propose a design methodology to suppress the EM information leakage from the PCB PDN.

Additive Manufacturing of a W -Band System-on-Package

Abstract: In this article, we demonstrate the design, fabrication, and characterization of a $W$ -band system-on-package (SoP). This package is fully additively manufactured using a chip-first process and aerosol jet printing. With this method, we implement a transceiver consisting of two bare die amplifiers for transmitted and received signals, a bare die switch, printed bypass capacitors, surface-mount resistors for biasing networks, and a printed patch antenna, operating between 77.1 and 79.0 GHz. The second patch antenna of the same design, fabricated simultaneously, is used to characterize the antenna performance alone and the packaged components. Package substrates (dielectrics), conductors, and interconnects are printed around bare die attached to a carrier. Thin-film bypass capacitor dielectrics were printed using multimaterial aerosol jet printing (MMAJP), where aerosols of barium titanate and polyimide inks are mixed in place to form a high $\epsilon _{r}$ polymer matrix nanocomposite film. $W$ -band interconnect performance is achieved using conformal-shaped ramp interconnects, allowing for frequency agnostic performance of the interconnect with no impedance discontinuity, within the physical limits of the printer. The antenna alone achieves a maximum gain of 6.7 dBi at 78.3 GHz, and the SoP achieves a gain of 16.4 dBi for the package. We estimate the package loss to be 2.8 dB or 0.6 dB/mm, including interconnects.

Jitter-Aware Economic PDN Optimization With a Genetic Algorithm

Abstract: This article proposes a jitter-aware decoupling capacitors placement optimization method that uses the genetic algorithm (GA). A novel method for defining the optimization target function in regard to power delivery network (PDN) and power source-induced jitter (PSIJ) optimization based on the GA-based tool is proposed. The proposed method can provide an optimum and economic solution for the number of decoupling capacitors to use in a PDN to reach the target impedance. Then, by modifying the optimization target function with our proposed method, an optimum solution of the number of decoupling capacitors regarding the PSIJ can be obtained. The PSIJ analytical expressions are derived in conjunction with a resonant cavity model that includes the coordinates of the decoupling capacitors and the PSIJ transfer function. The GA-based optimization algorithm with the proposed target function is first applied to optimize the number of decoupling capacitors regarding the PSIJ. Finally, the measured jitters from HSPICE simulation results are used to verify our optimization method such that both the simulated results and analytically calculated results support the efficiency of our proposed optimization method.

A 48-to-12 V Cascaded Resonant Switched-Capacitor Converter Achieving 4068 W/in 3 Power Density and 99.0% Peak Efficiency

Abstract: A 4-to-1 cascaded resonant switched-capacitor (ReSC) converter, comprising two cascaded 2-to-1 ReSC converters, has been demonstrated to have high efficiency and high power density in previous literature. This work explores the approaches to further improve the performance of the cascaded ReSC converter, including merging two phases of the first stage into one phase and reducing the intermediate decoupling capacitor. The impact of the intermediate capacitor on the interaction between two stages is studied. With the optimization of circuit structure, active and passive component selection, layout, etc., this converter achieves a power density of 4068 W/in3 under 48 V input and 60 A output. The converter also has high efficiency for the entire load range, achieving 99.0% peak efficiency and 97.9% full-load efficiency with gate drive loss included. Both power density and efficiency are superior to the state-of-the-art.

A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning

Abstract: This article presents a universal modular hybrid low-dropout regulator (MHLDO) to provide any desired combination of the power supply rejection ratio (PSRR) and power conversion efficiency (PCE) with in-compliance output ripple, load transient response, and operating range while minimizing losses and decoupling capacitor. The hybrid architecture eliminates the need for the fine quantization of the digital LDO power gates and prevents any associated limit cycle oscillation while keeping the overheads low. It is configurable at design-time and robustly self-adjusts across different operating points via a scalable architecture. The modular topology overcomes significant challenges of developing a large variety of analog and digital LDOs in order to meet the varying PSRR and power budget requirements for systems on a chip (SoCs) in scaled CMOS. A nonlinear control (NLC) feature provides an energy-efficient way to respond to fast load transients, while the dynamic clamp strength tuning (DCST) technique prevents unnecessary oscillations stemming from the input parasitic inductances and improves stability while lowering switching losses. The designed MHLDO provides a programmable PSRR capability of up to −42 dB with a quiescent current of less than 27.3 $\mu \text{A}$ as ALDO and a 133-mV worst droop against a >1-A/ns fast di/dt load change as DLDO. A new figure of merit (FoM) with improved accuracy demonstrates performance of 83 fs.

A 50–82 GHz broadband cascode-based power amplifier in 40 nm CMOS

Abstract: In this paper, we present a broadband two-stage cascode-based power amplifier (PA) in 40 nm CMOS technology that covers the ISM band applications at 60 GHz, E-band applications channels (71–76 GHz, 77 GHz, 81–86 GHz), and Automotive radar application at 77 GHz. The bypass capacitor at the gate of the upper transistor of the cascode, which controls the swing, stability, and gain compression significantly, is studied and optimized carefully. Furthermore, a holistic design approach is provided to further optimize the input, output and interstage wideband matching networks to simultaneously improve the output power and gain performance over the whole operating frequency band. The measurement results show a power gain of 13 ± 1.5 dB, a maximum power added efficiency (PAE) and output gain compression point (POut1dB) of 15% and 11 dBm, respectively, while consuming 130 mW. Additionally, the PA achieves low measured group delay variations of 20 ± 10 ps and small measured AM-PM distortion

Packaging A Top-cooled 650 V/150 A GaN Power Modules with Insulated Thermal Pads and Gate-Drive Circuit

Abstract: This paper focuses on the design of a 650 V/150 A gallium-nitride (GaN) power module. Direct bonded copper (DBC) is applied as the insulated thermal pad to dissipate the heat generated by the GaN dies, where ceramics is employed for the thermal pad insulation. Printed circuit board (PCB) on the top of the GaN dies integrates the auxiliary power supply, the gate drive circuits and the decoupling capacitors, which can help the parasitic inductance reduction in the gate drive loop and the power loop to reduce the overshoot voltage across gate to source and drain to source. The packaged module exhibits high-current capability (150 A), high-compactness (45*33*9.6 mm3) and excellent thermal impedance from junction to heatsink. Taking advantages of the integrated gate-drive circuit, the proposed power module has simpler interface for users compared to regular GaN HEMTs on the market, which only needs PWM signal and non-isolated power supply to drive. To verify the electrical performance and thermal performance presented above, both double pulse test (DPT) and thermal test are conducted. DPT at 450 V/150 A shows around 54 V voltage spike only, which makes the proposed module suitable for high-power EV on-board charger or motor drive inverters.

CH3NH3PbI3 as a radio frequency decoupling capacitor: interplay between Maxwell–Wagner polarization and a pseudo inductive response

Abstract: Frequency-dispersive impedance analysis of CH3NH3PbI3 perovskite is carried out under the external Direct current (DC) field to investigate the interplay of dielectric polarization and delocalized carrier transport. Switching of capacitance from positive to negative values is observed in the radio frequency range (42.1–42.5 MHz) for the external bias ranging from 0–4 V. The switching frequency outlined a decreasing trend with an increase in bias. Upon fitting the experimentally obtained dispersions, a bi-relaxation mechanism is unveiled. One of its constituents arises due to the typical Maxwell–Wagner interfacial polarization between the grain cores and boundaries and acts at the lower frequencies. The other one is manifested via hopping of delocalized carriers, resulting in a high frequency degenerative pseudo inductive response. The interference of these two mechanisms is manifested into an asymmetric Breit–Wigner–Fano profile of the dielectric susceptance spectra. The results are further elaborated from a theoretical point of view involving the energy band structure, electron localization function, and Mulliken charge distribution.

Multiport PDN Optimization With the Newton–Hessian Minimization Method

Abstract: This article proposes an optimization algorithm using the Hessian minimization method, based on the Newton iteration, to evaluate the effectiveness of the placement of multiple decoupling capacitors on a power/ground plane pair. The exact effective decoupling regions are obtained using the Newton iteration method for each decoupling capacitor. The impedance of the IC port is lower than the target impedance no matter where the decoupling capacitor is placed in this region. To optimize specific capacitor placements in this region, the Newton iteration, based on the Hessian matrix, is used to determine the location where the impedance of the IC port is minimized at the antiresonant frequency of the plane pair. This placement optimization algorithm allows for a decoupling design method that can also be applied to a PDN with multiple decoupling capacitors for multiple IC ports. Compared with the method of random selection from within the effective decoupling area, the method proposed here requires fewer decoupling capacitors and less computational time.

Power Delivery for Silicon Interconnect Fabric

Abstract: Silicon interconnect fabric (Si-IF) is a wafer-scale heterogeneous integration platform. This platform promotes a paradigm shift in system integration and packaging methods, providing a single hierarchy of integration between the dies and the platform. The Si-IF effectively replaces the interposer, pack­age, and printed circuit board. A power delivery methodology for high power wafer-scale systems (expected to dissipate up to 50 kW of power) is proposed in this paper. The proposed methodology includes three distinct power distribution topologies that are compared in terms of power loss, thermal consideration, and manufacturability. Compatible applications for each topology are also discussed. The electrical model, IR drop, and Ldi/dt noise, of each power distribution topology, are extracted and compared. Assuming a load voltage of 1 V, the three topologies exhibit a total voltage drop of, respectively, 16.68 mV, 9.62 mV, and 12.28 mV, corresponding to, respectively, 1.67%, 0.96%, and 1.23%. Hierarchical integration of decoupling capacitors is also described to ensure low voltage ripple (<5%) at the point of load. The electrical models of the power distribution topologies are verified using FEM and SPICE simulations.

Optimizing a Buck Voltage Regulator and the Number of Decoupling Capacitors for a PDN Application

Abstract: An optimization methodology to determine the best values of the compensation elements of a buck voltage regulator (VR) as well as the optimal number of decoupling capacitors in a power delivery network (PDN) application is proposed. A state average equivalent circuit model of the buck converter is employed. The proposed optimization methodology gradually finds the best compensation parameter values of a buck converter VR to meet some stability criteria in a PDN application. Additionally, the number of parallel decoupling capacitors in the PDN is minimized to simultaneously meet a frequency-domain impedance profile specification and a time-domain voltage droop requirement.

Enhancing On-die PDN for Optimal Use of Package PDN with Decoupling Capacitor

Abstract: In this paper, a method of enhancing the performance of on-die Power Distribution Network (PDN) and modeling of off-die PDN to utilize a maximum of package-level PDN solutions with decoupling capacitor have been proposed. To improve the on-die PDN performance, multi-stacked Cu-pillar bump RDL is provided for tighter connections between bumps and decoupling capacitor for sharing between switching instances. The proposed multi-stacked Cu-pillar bump RDL is a cost-effective solution to improve on-die PDN performance. However, reinforcing on-die PDN on active layers requires expensive and complex processes. The proposed off-die PDN modeling method can further secure the power integrity performance margin, especially when applying the decoupling capacitors. It is proposed to consider only the ground bumps in the IP area as the reference for power domain to which the decoupling capacitor is applied. This helps in revealing the potential PDN design issues of the IP.

Accurate Inductance Models of Mounted Two-Terminal Decoupling Capacitors

Abstract: The inductance associated with a decoupling capacitor is typically represented with a constant equivalent series inductance (ESL). In reality, this inductance depends on how the capacitor is mounted and on coupling to closely located structures, including the traces and vias connecting the capacitor to the power and return planes. Here, a method is proposed to quickly and accurately compute the inductance associated with decoupling capacitors and their connections to the power planes. We call this equivalent inductance ${\boldsymbol{L}_{\boldsymbol{above,decap}}}$ . It is calculated by partitioning the geometry into sub-models for the connections to the power and return planes and for the mounted capacitor and pads. The accuracy of the partitioning approach is demonstrated in simulation and experiments using two common decoupling capacitor layouts. Simulations are performed using the finite element method (FEM) and the partial element equivalent circuit (PEEC) method. The partitioning approach estimates the overall inductance associated with the decoupling capacitor and its connections to the power bus within 16% if the distance between the capacitor and reference plane (dielectric thickness) is not more than 6 mils. A simplified PEEC model was further developed which allows a user to estimate the inductance associated with the capacitor using closed-form expressions. This simplified model estimates the capacitor's inductance within 14% of the results found using FEM. The models presented in this work should help both the power distribution network tool designer as well as the design engineer to obtain more accurate inductance estimates than is possible using the manufacturer's ESL value.

Pin Impedance-Based Figure of Merit With Mutual Coupling (PMC-FOM) for Assessment of a Decoupling Capacitor on Polygonal Parallel Plates

Abstract: A novel pin impedance-based figure of merit with mutual coupling (PMC-FOM) is proposed for effectiveness assessment of a decoupling capacitor. The algorithm is based on the relative location of the capacitor on parallel plates and takes into account mutual coupling by extending the existing scalar expressions to matrix relations. New analytical relations are developed for the calculation of derivatives as required for the iterative solution of the problem. The relations for resonant parallel plates of regular shapes are extended to the practical case of polygonal shapes. It is demonstrated that a capacitor’s effective zone can hardly be delimited with a simple circle when mutual interaction with other capacitors is considered. In fact, the presence of other capacitors deforms the circular zone to an irregular contour. The proposed method is analyzed with several benchmark examples and the results are validated for efficiency and accuracy by comparing with alternate methods including a commercial electromagnetic (EM) simulator.

Optimizing On-Chip Decoupling Capacitors to Improve Power Supply Noise Induced Jitter and ESD Robustness

Abstract: The designs of power delivery network (PDN) and electrostatic discharge (ESD) protection are increasingly challenging and crucial in today's highly complicated silicon chips. The budgets of supply noise and PSIJ are significantly reduced. These stringent budgets and CDM ESD protection demand low-ESR on-chip decoupling capacitors to mitigate the problems. MIMcap usually provides an order of magnitude larger capacitance than any other on-die capacitance implementation. However, MIMcap typically has large ESR, which significantly reduces its effectiveness and hence needs to be optimized. MIMcap frequency response is extremely layout-dependent. In this paper, the methodologies of MIMcap optimization for various processes in different foundries are described. The methodologies are applied for the first time in three Intel FPGA silicon chips. The applications prove that the optimized MIMcap reduces ESR, PDN noise, PSIJ, and improves the ESD robustness. MIMcap optimization methodologies enable higher-performance and cost-competitive designs.

Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits

Abstract: The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (VDD) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the charged-device model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18- ${\mu }\text{m}$ CMOS technology.

Multi-Terminal Low-ESL 3D Silicon Capacitors as Enabler for Optimized and Flat PDN Design

Abstract: Both in Mobile and High-performance Computing (HPC) applications, efficient power supply of the processors was and is still being a big challenge for designers. Indeed, for these applications the power consumption is increasing while the power supply voltage is decreasing in alignment with the latest technological nodes (7nm, 5nm, 3nm…). Thus, lowering and flattening the Power Distribution Network (PDN) impedance is more than ever important to mitigate the voltage fluctuation, the resonance and anti-resonance peaks caused by the PDN's components. Such optimization is done by tuning the features of the different decoupling capacitors used along the power path from the power supply down to the processor. So, by increasing the capacitance, lowering the Equivalent Series Inductance (ESL) and adjusting the Equivalent Series Resistance (ESR) of the different decoupling capacitors, one can manage to have a very low and flat PDN impedance. An overview of the existing 3D Silicon Capacitors (Si-Cap) is presented. Comparison with classical decoupling components will be done and different assembly configurations are discussed (Die side, Embedded, Land side). These components bring unprecedented design flexibility and demonstrated significant improvements by reducing the voltage drop and enabling an efficient power noise reduction.

Metaheuristic Optimization of Decoupling Capacitors in a Power Delivery Network

Abstract: In VLSI circuits and systems, it is a common practice to reduce power supply noise in power delivery networks by decoupling capacitors. The optimal selection and placement of decoupling capacitors is crucial for maintaining power integrity efficiently. This paper presents a metaheuristic technique based generic framework for decoupling capacitor optimization in a practical power delivery network. The cumulative impedance of a power delivery network is minimized below the target impedance by optimal selection and placement of decoupling capacitors using state-of-the-art metaheuristic algorithms. A comparative analysis of the performance of these algorithms is presented with the insights of practical implementation.

Solving Power Integrity Challenges for Smart Computing Era

Abstract: To solve increasingly difficult power delivery issue for high-end 2.5D and 3D based smart computing systems, we propose the combined structure of backside PDN and integrated stack capacitor (ISC). Transistor shrinkage continues to deliver the performance needs for AI-enabled smart devices with relatively constant device size causing the power delivery path to be very narrow and resulting a severe IR-drop issue. The concept of backside PDN has recently been proposed to minimize the delivery path and IR drop. To further address AC noise, we propose using backside PDN with ISC. To simplify the analysis, we model the system using a lumped circuit and simulate on both frequency and time domains. In the simulation, we assume the simplest current scenario which assumes step pulse after idle state. ISC can be integrated in 2.5D and 3D systems in three different ways: discrete device, 2.5D silicon interposer, 3D Wafer-on-Wafer (WoW) integration. Our simulation assumes interposer-based ISC with backside PDN for a variety of analysis. As confirmed in the previous researches related to ISC, hundreds of MHz noise is effectively decreased. Applying of backside PDN decreases the voltage drop at the steady state as well.

Modeling of Power Supply Noise Associated with Package Parasitics in an On-Chip LDO Regulator

Abstract: In this paper, the power supply noise associated with package parasitics in an on-chip low-dropout (LDO) regulator is investigated. The on-chip LDO regulator with off-chip decoupling capacitors has power supply rail noise typically in the frequency range of few hundreds of MHz, which is related to the inductive package interconnects and the parasitic capacitance of the pass transistor. An equivalent circuit is proposed to model the power supply noise and understand the effect of inductive package interconnects. Based on the proposed equivalent circuit, the mitigation of the power supply noise from a package design perspective is discussed.

Power Delivery Network Impedance Profile and Voltage Droop Optimization

Abstract: The design process of power delivery networks (PDN) in modern computer platforms is becoming more relevant and complex due to its relationship with high-frequency effects on signal integrity. When circuits start operating, the changing current flowing through the PDN produces fluctuations creating voltage noise. Unsuccessful noise control can compromise data integrity. A suitable PDN design approach is the use of decoupling capacitors to lower the impedance profile and mitigate current surges, ensuring a small variation in the power supply voltage under significant transient current loads. An optimization approach to determine the number of decoupling capacitors in a PDN is presented in this paper, aiming at decreasing the amount of decoupling capacitors without violating the PDN design specifications, looking at both the impedance profile in the frequency domain and the resulting voltage droop in the transient time-domain.

A Modified Genetic Algorithm for the Selection of Decoupling Capacitors in PDN Design

Abstract: Decoupling capacitors are used to provide adequate and stable power for integrated circuits in printed circuit boards (PCB). For complicated and large designs, it is difficult to select capacitors to meet voltage ripple limits while also minimizing cost because the search space is too large. In this work, a new genetic algorithm (GA) is proposed for the selection and placement of capacitors to meet a target impedance using as few capacitors as possible. The GA is centered around controlling the number of unused port locations in the GA population solutions, with the result of smoothing out the GA convergence and speeding up the convergence rate. A result comparison is made of the proposed GA against other algorithms and found the GA competitive if not better for the select test cases.

Efficient Estimation of Noise Suppression Amount in Power Bus with Decoupling Capacitors Using Lossy Resonator Filters

Abstract: To estimate the amount of noise suppressed by lossy resonator filters (LRFs) in a power bus with a decoupling capacitor, we used an equivalent circuit model considering the effect of the capacitor to know the suppression mechanism using the LRF. The discrepancy between the model and a full-wave simulation was approximately 2 dB.

Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip

Abstract: This article examines the signal integrity problem arising due to resistive drop, inductive noise and electro- migration, causing voltage fluctuations known as supply noise in an integrated circuit. Insertion of decoupling capacitor is a commonly used technique for reducing the supply noise. In this article symbiotic organism search (SOS) algorithm is used to estimate the decap. Another relevant issue addressed is the distribution of the decap over the chip. To get the best possible results in the post-layout stage pruning technique is used for partitioning and particle swarm optimization (PSO) algorithm is applied in the floorplanning stage. The purpose of this work is to reduce the supply noise without much affecting other design parameters of the chip. Simulation results show that supply noise has been reduced by up to 74.07% and the decap budget has been reduced by up to 37.4%. This approach can be used for any system-on-chip.

Analysis of Electromagnetic Information Leakage from Overdesigned Power Delivery Network of Cryptographic Devices

Abstract: In this paper, an analysis of electromagnetic (EM) information leakage from an overdesigned power delivery network (PDN) of cryptographic devices is presented. In the target hierarchical PDN, sufficient decoupling capacitors are mounted in both on-chip and printed circuit board (PCB) PDNs which maintained the hierarchical PDN impedance below a target impedance from 1 MHz to 1 GHz. Correlation electromagnetic analysis (CEMA) and secret key extraction are conducted based on measured electric and magnetic field radiations from various locations in the hierarchical PDN such as above chip, PCB PDN, and decoupling capacitors. For the first time, it is verified that a cryptographic device complying with the target impedance specification with a sufficient impedance margin can leak full-byte secret key information via EM field radiation. Based on the analysis result, the PDN design methodology for the cryptographic device is presented.