Showing papers on "Decoupling (electronics) published in 1996"

Control topology options for single-phase UPS inverters

Abstract: Several control topologies for single-phase UPS inverters are presented and compared, with the common objective of providing a dynamically stiff, low THD, sinusoidal output voltage. Full state feedback, full state command controllers are shown utilizing both filter inductor current and filter capacitor current feedback to augment output voltage control. All controllers presented include output voltage decoupling in a manner analogous to "back-EMF" decoupling in DC motor drives. Disturbance input decoupling of the load current and its derivative is presented. An observer-based controller is additionally considered, and is shown to be a technically viable, economically attractive option. The accuracy transfer function of the observer estimate is used to evaluate its measurement performance. Comparative disturbance rejection is evaluated by overlaying the dynamic stiffness (inverse of output impedance) frequency response of each controller on a single plot. Experimental results for one controller are presented.

Decoupling the multiconductor transmission line equations

Abstract: A comprehensive discussion is presented of the method of decoupling the multiconductor transmission line (MTL) equations by the method of transformation of the voltages and currents to mode voltages and currents in order to obtain their general solution. Various ways of defining and obtaining the transformations are shown which serve to connect the myriad of such definitions and also point out where inconsistencies in those definitions can result. Structures for which the decoupling is assured are also discussed. The MTL equations to be decoupled are in the frequency domain, and extensions to their applicability in the time-domain are shown.

A novel integrated decoupling capacitor for MCM-L technology

Abstract: This paper discuses the design, materials, fabrication and measurements of a novel integrated decoupling capacitor for MCM-L-based substrates. Based on modeling using the SLA Roadmap, it has been estimated that 13-72 nF/cm/sup 2/ of specific decoupling capacitance will be required for the next decade. The capacitor in this paper addresses this need. The fabrication of the capacitor has been achieved using filled polymer materials in thin film form, with via diameters of 100 um and below, through photodefinable processes. Dielectric constant as high as 65 with loss tangent below 0.05 and specific capacitance of 22 nF/cm/sup 2/ have been achieved. The scattering parameters were measured up to 20 GHz using a network analyzer for various capacitor structures to study input impedance and scaling of the devices. Input impedance of the capacitor is found to be low in the GHz range. The polymer-filled materials and capacitor structures are also scalable to a variety of sizes and values.

Testing historical hypotheses of morphological change: biomechanical decoupling in loricarioid catfishes.

Abstract: The "decoupling hypothesis" has been proposed as a mechanistic basis for the evolution of novel structure and function. Decoupling derives from the release of functional constraints via loss of linkages and/or repetition of individual elements as redundant design components, followed by specialization of one or more elements. Examples of apomorphic decoupling have been suggested for several groups of organisms, however there have been few empirical tests of explicit statements concerning functional and morphological consequences of decoupling. Using the loricarioid catfishes, we tested one particular consequence of decoupling, the prediction that clades possessing decoupled systems having increased biomechanical complexity will exhibit greater morphological variability of associated structures than outgroups having no such decoupled systems. Morphometric procedures based on interlandmark distances were used to quantify morphological variance at three levels of design at successive nodes in the loricarioid cladogram. Additional landmark-based procedures were used to localize major patterns of shape change between clades. We report significantly greater within-group morphometric variance at all three morphological levels in those lineages associated with de- coupling events, confirming our predictions under the decoupling hypothesis. Two of 12 comparisons, however, yielded significant variance effects where none were predicted. Localization of the major patterns of shape change suggests that disassociation between morphological and functional evolution may contribute to the lack of fit between variance predictions and decoupling in these two comparisons.

Method and apparatus for coupling multiple independent on-chip Vdd busses to an ESD core clamp

Abstract: A single clamp circuit for integrated circuits with multiple V dd power pins by coupling the various V dd busses to an ESD clamped V dd bus or pseudo- V dd bus via diodes. The diodes will provide coupling from any V dd bus to the clamp circuit during a positive ESD transient. A diode for each V dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses. To help filter small signal noise and provide an additional charged device model discharge path, a capacitor is added from the pseudo or ESD V dd to substrate ground. Also disclosed is an ESD protection scheme for allowing a pad voltage to exceed the power supply voltage without using an avalanching junction as the ESD protection means. Further disclosed is a clamp scheme for allowing the transistors of the power supply clamp to see voltages lower than that of the pad voltage which exceed the process reliability limits.

Method of making a structure for providing signal isolation and decoupling in an integrated circuit device

Abstract: A signal isolation and decoupling structure fabricated in an integrated circuit device for providing signal isolation and decoupling for signal carrying conductors of the integrated circuit device, wherein one of the conductors is embedded in dielectric material and enclosed within an isolation structure of an electrically conductive material which is formed in the integrated circuit device and extends substantially the length of the conductor, the isolation structure including top and bottom walls of electrically conductive material and first and side walls, also of an electrically conductive material, which electrically interconnect the top and bottom walls, forming an enclosure around the conductor. Also described is a method for fabricating the isolation structure in the integrated circuit device.

Integrated high-performance decoupling capacitor

Abstract: An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance. Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip. Very precise decoupling of selected areas in the chip circuit can be achieved by forming precise and multiple metal deposits of either the same size or of varying sizes to define specific capacitances and individually connecting these deposits to the circuit areas needing the precise decoupling capacitance.

Optimum placement of decoupling capacitors on packages and printed circuit boards under the guidance of electromagnetic field simulation

Abstract: This paper presents an efficient signal integrity analysis technique for simulating voltage fluctuations on power/ground planes in complex packaging structures. With its unique circuit and electromagnetic field solvers, the value, the number and the location of the decoupling capacitor placed on packages or printed circuit boards can be quickly and effectively evaluated. Examples are provided to demonstrate that how a good decoupling scheme is achieved under the guidance of electromagnetic field simulation.

A voltage control strategy for current-regulated PWM inverters

Abstract: Alternative voltage control strategies for current-regulated PWM inverters are analyzed, including previously established feedforward and feedforward/feedback controllers and a newly proposed decoupling feedback control strategy. The steady-state and dynamic characteristics of each of these control methods are illustrated and compared for a selected inverter design. It is shown that the feedforward controller exhibits steady-state error and an undesirable overshoot of the output voltages during startup. The addition of a feedback loop eliminates the steady-state error and reduces the overshoot; however, the natural response is underdamped regardless of the choice of feedback gains. A decoupling feedback control strategy that eliminates the disadvantages of the feedforward and feedforward/feedback controllers is described. Using the decoupling feedback controller, it is possible to eliminate the steady-state error and place the closed-loop poles wherever desired. Moreover, if the closed-loop poles are selected appropriately, it is possible to eliminate the overshoot of the output voltages during startup transients.

Semiconductor device with increased on chip decoupling capacitance

Abstract: A semiconductor device has an on-board decoupling capacitor provided at its interconnect region. The decoupling capacitor comprises two layers of metallurgy separated by a dielectric layer wherein two of the layers are identically patterned.

Decoupling capacitor for integrated circuit signal driver

Abstract: A decoupling capacitor for an integrated circuit and method of forming the same. The decoupling capacitor includes a p-channel device having first and second p-type doped diffusion regions, a device channel region therebetween, a device gate overlying the device channel region, and a gate insulator separating the device gate and channel region. The first and second diffusion regions are electrically connected to a positive power supply, and the device gate is electrically connected to a negative power supply. The decoupling capacitor may be formed proximate a signal driver in the integrated circuit. The decoupling capacitor may be formed without additional, expensive semiconductor fabrication steps and operates to minimize noise in the circuit.

Lighting device for motor vehicle

Abstract: The device (10) has a light guide (14), and another light guide (16) arranged adjacent to the former light guide. The light guides comprise longitudinal sides (24, 30) with sets of decoupling elements (26, 32), respectively. The decoupling elements are provided with respective light emitting surfaces (28, 34) that are separated from each other by recesses. The light guides are arranged relative to each other such that the side of the latter light guide lies opposite to the side of the former light guide. Light sources (18, 20) i.e. LEDs, are coupled to the respective light guides.

High frequency characteristics of MCM decoupling capacitors

Abstract: The increased frequency operation of CMOS microprocessors and other circuitry places severe demands on power distribution systems to supply stable, noise-free power. Particularly in MCMs, where short signal line lengths allow fast off-chip switching, improved decoupling capacitors are required for short-term charge storage to reduce dI/dt noise. This paper examines the relative parasitic contributions of off-chip connections, MCM power distribution planes, and decoupling capacitors, and the effect of these parasitics on power distribution integrity. It is shown that the effect of the inductances of chip-to-substrate interconnections can be minimized by using multiple interconnections and careful design both in a wirebond or in a flip chip environment. Similarly, the intrinsic inductance and resistance of power distribution planes, either solid, perforated, or the new IMPS (Interconnected Mesh Power System), is extremely low and does not determine the effectiveness of power distribution.

Minimizing chip-level simultaneous switching noise for high-performance microprocessor design

Abstract: This paper describes the on-chip power bus modeling and switching noise analysis for high performance circuit design, and the methodology to minimize simultaneous switching noise by optimizing the placement of on-chip decoupling capacitors. The switching noise is analyzed at both the package level and the chip level. An equivalent circuit which consists of time-varying resistors, loading capacitors, and decoupling capacitors, is used to simulate the switching activities of functional blocks. Both the resistive and inductive voltage drops on the power bus are modelled to identify the hot spots on the chip and /spl Delta/V across the chip. Based on the noise analysis results, we can determine the amount of decoupling capacitance needed to keep the power supply voltage within specification, and optimize the final size and location of on-chip decoupling capacitors.

Method for testing semiconductor packages using decoupling capacitors to reduce noise

Abstract: A method for the testing semiconductor packages is provided. The method includes electrically connecting a decoupling capacitor directly to the leads of the semiconductor package being tested, or alternately, directly to contact members of an electrical connector for the package. The decoupling capacitor is formed as a thin film capacitor that is mounted on the electrical connector of a testing apparatus such as a burn-in board. In an illustrative embodiment, the decoupling capacitor is configured with a power contact that contacts the Vcc lead for the package and a ground contact that contacts the Vss lead for the package. The decoupling capacitor functions to reduce power supply noise and spurious signals during testing of the integrated circuits formed on the semiconductor die contained within the package.

Scan register with decoupled scan routing

Abstract: A scan register (80) provides for the decoupling of the scan data output signal (117) from the data output signal (116). This is provided through a tri-statable device (88), which is controlled by a scan enable signal or by the scan clock signal.

Decoupling compensation for the Apache helicopter

Abstract: The design of a decoupling compensator for the Apache helicopter is presented. The design is based on linear quadratic regulation with implicit model following. A decoupling compensator is designed for a reduced-order linear model of vehicle dynamics at hover using eigenstructure assignment. The resulting closed-loop system is used as a reference model in the design of a compensator for the full-order system, resulting in a constant state feedback matrix. A feedforward matrix (command mixer) is then designed to diagonalize the system at low frequencies. The design is evaluated with both the full-order linear model and a nonlinear simulation, ARMCOP. It is found to provide desired bandwidth and good decoupling properties with the linear model. The nonlinear simulation shows increased coupling due to the nonlinearities.

BaSrTiO/sub 3/ thin films for integrated high frequency capacitors

Abstract: The complex oxide dielectric Ba/sub 1-x/Sr/sub x/TiO/sub 3/ (BST) has recently been studied intensively for DRAM applications. Another significant nearer term application for which BST may be suited is replacement of discrete capacitors now attached to advanced IC's. Specific devices include bypass, decoupling, and switched filter capacitors, often operated at high frequencies. With current SiO/sub 2/ based dielectrics such integrated capacitors may take up from 20% to 50% of the device area; use of higher dielectric constant BST could reduce this by at least a factor of 10. We will discuss properties of MOCVD-grown BST which relate to these capacitor applications, including second order dielectric nonlinearity and leakage currents at useful device operating voltages (3 V). Dielectric constant, nonlinearity and breakdown voltages are found to have a strong dependence on deposition temperature of BST films, so optimum processing conditions will depend on the end device application.

Static controllers for magnetic suspension and balance systems

Abstract: For a test aircraft in a wind tunnel with magnetic suspension and balance systems, a decoupling control configuration is proposed. Using the input–output decoupling technique the flight variables are controlled independently at all frequencies and for all aerodynamic and electromagnetic conditions. The decoupling controllers are static. The performance of the resulting closed-loop system is quite satisfactory.

Integrated Decoupling Capacitors Using Pb(Zr,Ti)O3 Thin Films

Abstract: Thin-film decoupling capacitors based on ferroelectric PLZT (PbLaZrTiO{sub 3}) films are being developed for advanced packaging. The increased integration that can be achieved by replacing surface- mount capacitors should lead to decreased package volume and improved high-speed performance. For this application, chemical solution deposition is an appropriate fabrication technique since it is a low- cost, high-throughput process. Relatively thick Pt electrodes (1{mu}m) are used to minimize series resistance and inductance in fabricating these devices. Also, important electrical properties are discussed, with emphasis on lifetime measurements, which suggest that resistance degradation will not be a severe limitation on device performance. Finally, some of the work being done to develop methods of integrating these thin-film capacitors with integrated circuits and multichip modules is presented.