Showing papers on "Decoupling (electronics) published in 1998"

Resonance and damping in CMOS circuits with on-chip decoupling capacitance

Abstract: Design of on-chip decoupling capacitance and modeling of resonance effects in the power supply network of CMOS integrated circuits is addressed. The modeling is based on mathematical limits proving that damping will be low, resulting in resonance unless careful design is used. Design strategies that reduce resonance are discussed. It is shown that an optimal parasitic resistor in series with the decoupling capacitor gives a maximum damping factor of 0.5 and practical values are within the range 0.3-0.4. Examples of digital circuits show that proper design of on-chip decoupling capacitance may reduce the number of bonding wires by an order of magnitude. The modeling and design suggestions are also applicable to mixed-mode circuits. In particular, sampled analog networks benefit with a potentially higher sampling rate if enhanced damping is introduced during design.

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Abstract: Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBM's CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Substrate interconnect for power distribution on integrated circuits

Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

Economic and technical viability of integral passives

Abstract: Integral substrates (printed wiring boards with buried capacitors and/or resistors) can lower costs, improve component density, improve performance and reliability. Integral substrates are economically and technically viable for replacing a large portion of the ceramic chip capacitors used for decoupling and resistor chips and networks used for termination, pull-up and pull-down. However, passive integration is easier said than done. Integral substrates require new design and test systems, manufacturing processes and materials. Further investigation concludes that stable, low cost materials and processes, design and test systems are only half the equation. In order for this technology to reach its full market potential, time-to-market issues such as rapid prototyping and engineering changes must be solved.

Investigation of candidate VRM topologies for future microprocessors [voltage regulator modules]

Abstract: Future generation microprocessors are expected to exhibit much heavier loads and much faster transient slew rates. Today's voltage regulator module (VRM) will need a large amount of extra decoupling and output filter capacitors to meet future requirements, which basically makes the existing VRM topologies impractical. In this paper, a candidate topology, interleaved quasi-square wave, is proposed. Its design, simulation and experimental results are presented.

ESR and ESL of ceramic capacitor applied to decoupling applications

Abstract: Power distribution system noise affects computer product timing performance, signal integrity and electromagnetic interference. Between 1 MHz and 1 GHz, the primary means of reducing power distribution noise is with ceramic decoupling capacitors. To achieve a certain target impedance, it is important to characterize the ESR of ceramic decoupling capacitors, as this directly determines the number of capacitors required on a board. A new technique to extract ESR is described in this paper. Another factor which determines the capacitance value of decoupling capacitors is the ESL (equivalent series inductance) associated with capacitors mounted on a PCB. A study that compares the ESL of different pad layout geometries is also presented.

Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission

Abstract: Recently, electromagnetic interference (EMI) and radiated emission has become a major problem for high-speed circuit and package designers, and it is likely to become even severe in the future. However, until recently, designers of integrated circuit and package did not give much consideration to electromagnetic radiated emission and interference in their designs. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital system and boards. However, there has not been a systematic study to understand the effects of on-chip and off-chip decoupling capacitors on the electromagnetic radiated emission. In this paper, we report the simulation and the measurement results regarding the radiated emission due to the power/ground bounce. And we discuss the effects of the on-chip and off-chip decoupling capacitors to the power/ground bounce and the electromagnetic radiated emission. This circuit is simulated using HSPICE. Test ICs and printed circuit boards were designed and fabricated. Using a transverse electromagnetic (TEM) cell, the radiated electric field of the device under test (DUT) is measured. Combined placement of the on-chip and off-chip decoupling capacitor achieves more than 10 dB suppression of the radiated emission on the whole spectrum region. The design rule of the optimum placement of the decoupling capacitor was obtained.

Economic and technical viability of integral passives

Abstract: Integral substrates (printed wiring boards with buried capacitors and/or resistors) can lower costs, improve component density, improve performance and reliability. Integral substrates are economically and technically viable for replacing a large portion of the ceramic chip capacitors used for decoupling and resistor chips and networks used for termination, pull-up and pull-down. However, passive integration is easier said than done. Integral substrates require new design and test systems, manufacturing processes and materials. Further investigation concludes that stable, low cost materials and processes, design and test systems are only half the equation. In order for this technology to reach its full market potential, time-to-market issues such as rapid prototyping and engineering changes must be solved.

Developing a decoupling methodology with SPICE for multilayer printed circuit boards

Abstract: As CPU and bus speeds increase in high end workstation computer systems, signal integrity and EMI issues related to delta-I noise (caused by the current demands of the many fast switching devices on the PCB) require serious consideration during the design process. Historically, decoupling caps have been deployed "randomly" about the PCB in an attempt to mitigate this noise. However, as clock speeds increase beyond 500 MHz and rise times decrease to less than 300 psec, the design of power bus decoupling on multilayer boards requires close attention. Issues such as interplane capacitance, decoupling capacitor placement values and quantities, interconnect inductance as well as power bus resonances all need to be carefully manipulated and controlled in order to achieve the most cost effective and robust electromagnetically compatible products. In this paper a SPICE model is employed to examine the impedance of a typical power bus on a multilayer PCB. This impedance is calculated at numerous points (or nodes) around the board with respect to the noise sources and as a result the choice and quantity of decoupling capacitors as well as placement information and the resulting impact on the power supply impedance is evaluated.

Low inductance power distribution system for an integrated circuit chip

Abstract: A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board. The decoupling capacitors have positive and negative electrodes are electrically coupled to the power and ground plated through holes respectively. The C4 power and ground bumps, the power and ground carrier vias, the power and ground carrier via subgroups, the power and ground solder balls, the contact pads, the power and ground plated through holes, and the positive and negative electrodes are arranged in anti-parallel tessellations to reduce the inductance of a loop circuit from the decoupling capacitors to the integrated chip circuit.

Integrated circuit device with integral decoupling capacitor

Abstract: A flat, thin decoupling capacitor is disposed inside an integrated circuit device in a coplanar relationship with a semiconductor chip and a bonding element When connected to the power and ground plane of a device substrate or in a leadframe device, the decoupling capacitor is positioned close to the semiconductor chip to substantially reduce ground bounce and crosstalk from the semiconductor chip When the decoupling capacitor is positioned to locate the semiconductor chip between itself and the device substrate or leadframe device, the decoupling capacitor shields electromagnetic interference from the semiconductor chip

Calorimetric apparatus for measurement of power losses in capacitors

Abstract: A calorimetric apparatus has been designed especially for measurement of losses in capacitors. The original feature of this determination of capacitor losses lies in the use of the isothermal calorimetry and in the measurement of an electrical power and not of a temperature rise. The accuracy of the method is very good and is independent of the value of the capacitor dissipation factor, it is very useful for capacitors with very low losses. The Equivalent Series Resistance of polymer film capacitors, using polypropylene, polycarbonate, and polyethylene terephtalate, have been determined under rated voltage, in the rang 1 kHz-1 MHz, between 220 K and 370 K. The losses in the dielectric material have been separated from the losses in the metallic parts and their variations with temperature and frequency have been studied. Unlike electrical devices, the calorimetric apparatus allows us to carry out measurements of power losses in capacitors used for power electronic application (filtering, decoupling), under non-sinusoidal applied voltages.

A compact dual‐port, dual‐frequency printed antenna with high decoupling

Abstract: Reference LEMA-ARTICLE-1998-006View record in Web of Science Record created on 2006-11-30, modified on 2016-08-08

Modeling multilayered PCB power-bus designs using an MPIE based circuit extraction technique

Abstract: A circuit extraction tool (CEMPIE) has been developed based on the mixed-potential integral equation (MPIE) using a quasi-static approximation. A power-bus in a multi-layered PCB consisting of a pair of dedicated ground and power planes is studied using this tool. The distributed behavior of a power-bus is represented by a collection of passive circuit elements, which is valid up to several gigahertz. The decoupling performance of a power-bus due to its layer spacing and the dielectric constant is evaluated for simple test geometries. The impact of the relative distance between the noise source and the potential receiver is also studied. Novel structures such as a power island were studied in both thin and thick boards, and the decoupling performance due to the locations and values of the decoupling capacitors were also investigated.

Acoustical barrier with ribbed decoupler

Abstract: An acoustical barrier for blocking the transfer of sound through a barrier wall. The acoustical barrier comprises a sound absorbing layer and a decoupling layer mounted to the sound absorbing layer and spacing the sound absorbing layer from the barrier wall. The decoupling layer has a constructoin defining multiple voids to reduce the quantity of material used to construct the decoupling layer and to reduce the surface area of the decoupling layer contracting the barrier wall. Preferably, the decoupling layer has multiple protrusions such as ribs between which are interstitial spaces defining the voids.

A new methodology for the stability analysis of large-scale power electronics systems

Abstract: A new methodology is proposed to investigate the large-signal stability of interconnected power electronics systems. The approach consists of decoupling the system into a source subsystem and a load subsystem, and stability of the entire system can be analyzed based on investigating the feedback loop formed by the interconnected source/load system. The proposed methodology requires two stages: 1) since the source and the load are unknown nonlinear subsystems, system identification, which consists of isolating each subsystem into a series combination of a linear part and a nonlinear part, must be performed; and 2) stability analysis of the interconnected system is conducted thereafter based on a developed stability criterion suitable for the nonlinear interconnected source-load model. Applicability of the methodology is verified through the stability analysis of a typical power electronics system.

Selectable power supply lines for isolating defects in integrated circuits

Abstract: An integrated circuit providing selectable power supply lines for isolating defects manifested by unusual quiescent current levels. During normal operation, a unitary power supply line provides power to different sections of the integrated circuit. In accordance with the present invention, the unitary power supply line is decoupled from the sections of the integrated circuit and power is provided by the selectable power supply lines during failure analysis of the integrated circuit. A section of interest of the integrated circuit is first placed in a static test state in which defects in the section may produce unusual quiescent current levels. A selectable power supply line for providing power only to the specified section of the integrated circuit is the activated by an enable signal provided to a switch coupled to the selectable power supply line. The switch allows for decoupling of the unitary power supply line from the selectable power supply line. By powering the section of interest with a dedicated power supply line, automated test equipment (ATE) can be utilized during production testing to identify areas of unusual quiescent current consumption and defect localization time for the integrated circuit is significantly reduced.

Filtrations in feedback synthesis: Part II – Input-output decoupling and disturbance decoupling

Abstract: Abstract The input-output decoupling problem and the disturbance decoupling problem are solved using the general feedback setting introduced in E. Delaleau and P. S. Pereira da Silva, Filtrations in feedback synthesis: Part I – Systems and feedbacks, Forum Math. 10 (1998) 147–174. Necessary and sufficient rank conditions are supplied, showing that endogenous state feedback is sufficiently general in order to solve these problems for generalized dynamics. The deffnitions of feedback of the first part of the paper are extended for considering the disturbed case, i.e., the case where dynamics are influenced by disturbances. For classical dynamics, most commonly considered in the literature, quasi-static state feedback is in fact rich enough for solving these problems. This kind of feedback, which is in between the static and the general dynamic feedback, does not require the integration of any differential equation.

Medical fluid line arrangement

Abstract: A medical fluid line arrangement includes coupling elements 3,4 engageable in a coupled configuration, the respective coupling elements being decoupled upon a predetermined separating force acting to separate the coupling elements. The coupling elements 3,4 are fitted to respective cut ends of a cut tube 1. Fluid is permitted to flow through the engaged coupling elements; the coupling elements typically seal the relevant end of the respective fluid line element, upon decoupling. The level of the force required to effect decoupling may be varied.

Shaft decouple logic for gas turbine

Abstract: The present invention is addressed to a control logic for determining the occurrence of shaft decoupling in a gas turbine engine. The control logic in the preferred embodiment receives inputs for shaft rotational speed and/or compressor pressure and uses these parameters for making a determination of shaft decoupling in fractions of a second, before serious damage to the gas turbine engine can occur. The control logic also utilizes multiple interval sampling, and sampling over multiple channels to verify any determination of shaft decoupling. Once a shaft decouple has been verified, fuel flow to the engine is cut off, thus shutting down the engine.

Fast current control for low harmonic distortion at low switching frequency

Abstract: The structure of the current control loop of an induction machine drive determines decisively the dynamic performance of the overall system. Fast current control is a prerequisite for dynamic decoupling between the torque and the flux commands. Standard solutions are well established for drives in the low- and medium-power ranges. The low switching frequency of high-power pulsewidth modulation inverters calls for a tradeoff in controller design between the low harmonic losses and torque ripple in the steady state on one hand, and fast dynamic response during the transients on the other. The problem is developed in detail. A variable-structure approach is proposed as the solution.

Modular air jet array with coanda exhausting for module decoupling

Abstract: A decoupling mechanism is provided for passively or actively decoupling an exhaust from a modular air transport system by diverting an amount of air exiting a channel in a first module in a direction other than the process direction through use of the Coanda effect. This decouples the amount of air from a downstream module. This is achieved by providing edge surfaces of the channel outlet, formed on top and bottom plates of the first air module, so that one of the two edge surfaces has a larger radius of curvature than the other. An air vent formed by a gap between the other of the edges and the second module is also provided to assist in the Coanda effect.

Designing power bus decoupling for CMOS devices

Abstract: The adequacy of the DC power bus decoupling for CMOS devices can be determined if the effective board decoupling capacitance, the CMOS load capacitance, the CMOS power dissipation capacitance, the switching time, and the allowable bus noise voltage are known. A simple method is presented for estimating the effective decoupling capacitance. The load and power dissipation capacitance values are shown analytically and experimentally to be closely related to the transient current. The transient current and switching time are used to estimate the transient noise voltage on the power bus.

Method and system for measuring equivalent series resistance of capacitors and method for decoupling power distribution systems

Abstract: A system and method for measuring the equivalent series resistance (ESR) of one or more capacitors using an impedance analyzer, whereby the capacitors are joined to the impedance analyzer with a conductive adhesive. The conductive adhesive may advantageously provide for an electrically and mechanically stable connection between the capacitor and the remainder of the electrical circuit used to measure the ESR of the capacitor. The conductive adhesive may include heat activated or cold solder, or conductive putty. The system comprises a measuring unit for sweeping a frequency range to find the minimum impedance for the capacitor and a connector assembly for holding the capacitor in an electrically and mechanically stable connection using the conductive adhesive. The connector assembly includes a mating portion adapted for electrically connecting the connector assembly to an I/O port of the measuring unit and a terminal portion that accommodates a connection to the capacitor using the conductive adhesive. The method comprises connecting a mating portion of the connector assembly to the impedance analyzer. Next, the impedance analyzer is calibrated, and the capacitor is then connected to a terminal portion of the connector assembly using the conductive adhesive. Finally, the impedance analyzer sweeps a frequency range to find the ESR for the capacitor. The method may also measure the ESR of each of a number of capacitors using an impedance analyzer. The method may connect in series the number of capacitors to the connector assembly using the conductive adhesive. The method determines the equivalent series resistance of each of the number of capacitors by dividing the minimum impedance by the number of capacitors. The method may also comprise selecting one or more capacitors, measuring the ESR of each of the capacitors, and determining a desired number of each of the capacitors for placing into a power distribution system.