Showing papers on "Degree of parallelism published in 1985"
TL;DR: This paper addresses the problem of efficiently computing the motor torques required to drive a manipulator arm in free motion, given the desired trajectory—that is the inverse dynamics problem and presents two "mathemati cally exact "formulations especially suited to high-speed, highly parallel implementations using VLSI devices.
Abstract: This paper addresses the problem of efficiently computing the motor torques required to drive a manipulator arm in free motion, given the desired trajectory—that is the inverse dynamics problem. It analyzes the high degree of parallelism inherent in the computations and presents two "mathemati cally exact "formulations especially suited to high-speed, highly parallel implementations using VLSI devices. The first method presented is a parallel version of the recent linear Newton-Euler recursive algorithm. The time cost is linear in the number of joints, but the real-time coefficients are re duced by almost two orders of magnitude. The second formu lation reports a new parallel algorithm that shows that it is possible to improve on the linear time dependency. The real time required to perform the calculations increases only as the [log2] of the number of joints. Either formulation is sus ceptible to a systolic pipelined architecture in which complete sets of joint torques emerge at successive intervals of f...
136 citations
01 Nov 1985
TL;DR: Concurrency aspects of ADA are presented as a case study of a state-of-the-art programming language and the problems of synchronization and communication includes semaphores, messages and mailboxes, and monitors.
Abstract: This paper surveys concurrency issues of programming languages. The evolution of these issues is analyzed in the context of the evolution of other language concepts, such as data and control abstraction. Specific concurrency concepts discussed in the paper include: granularity of parallelism, degree of parallelism, synchronization and communication, and physical distribution. The review of the problems of synchronization and communication includes semaphores, messages and mailboxes, and monitors. Concurrency aspects of ADA are also presented as a case study of a state-of-the-art programming language.
12 citations
IBM1
TL;DR: It is shown that as the number of independent arms approaches infinity, the degree of parallelism is bounded, and it is demonstrated that under conditions of spatial contention, there is little merit in having more than two independent arms at a work cell.
Abstract: When multiple independent robot arms attempt to perform concurrent operations at the same work cell, spatial interference imposes limits on the degree of parallelism that can be achieved. It is shown that as the number of independent arms approaches infinity, the degree of parallelism is bounded. Mathematical limiting values are derived for the extent of parallelism for two cases of an idealized simplistic application. The main value of these results is to demonstrate that under conditions of spatial contention, there is little merit in having more than two independent arms at a work cell. Designing the work cell to reduce contention increases the value of multiple independent arms.
10 citations
01 Feb 1985
TL;DR: This thesis explores the issues involved in developing a framework for circuit simulation which exploits the locality exhibited by circuit operation to achieve a high degree of parallelism, and designed and implemented the circuit simulator PRISM.
Abstract: Integrated circuit technology has been advancing at a phenomenal rate over the last several years, and promises to continue to do so. If circuit design is to keep pace with fabrication technology, radically new approaches to computer-aided design will be necessary. One appealing approach is general purpose parallel processing. This thesis explores the issues involved in developing a framework for circuit simulation which exploits the locality exhibited by circuit operation to achieve a high degree of parallelism. This framework maps the topology of the circuit onto the multiprocessor, assigning the simulation of individual partitions to separate processors. A new form of synchronization is developed, based upon a history maintenance and roll back strategy. The circuit simulator PRISM was designed and implemented to determine the efficacy of this approach. The results of several preliminary experiments are reported, along with an analysis of the behavior of PRISM.
8 citations
TL;DR: The fundamental structure of Fastbus and details of its basic operations are presented and it is shown that both high and low speed devices can be accomodated.
6 citations
01 Mar 1985
TL;DR: The design issues and the performance evaluation of a special purpose hardware recognizer device capable of performing pattern matching and text retrieval operations and the VLSI design and the time and space complexities of the proposed organization are discussed.
Abstract: This paper addresses the design issues and the performance evaluation of a special purpose hardware recognizer device capable of performing pattern matching and text retrieval operations. In addition, the VLSI design and the time and space complexities of the proposed organization are discussed. The structure of the system is based on the concept of the non-deterministic finite state model with a high degree of parallelism incorporated into the design. The system simulates a parallel finite state automaton by utilizing a number of identical units called “CELLs” which have associative processing capabilities.The proposed system improves the performance of pattern matching operations by matching several patterns in parallel. Because of the similarities between the scanning process during compilation and the pattern matching operations, the proposed module can be used as a hardware scanner. The hardware scanner can be used as an interface between the user and the compiler in the conventional general purpose systems as well as the language oriented or high-level language computers.
2 citations
TL;DR: A new type of list-processing oriented data flow machine is presented which achieves pipelined processing among activated functions and can utilize a high degree of parallelism even for simple programs due to the partial function-body execution and lenient cons effects.
Abstract: This paper describes some issues of parallel list processing under data flow control. Also a new type of list-processing oriented data flow machine is presented which achieves pipelined processing among activated functions. Performance evaluation through software simulation gave the following conclusions.
(1) This machine can utilize a high degree of parallelism even for simple programs due to the partial function-body execution and lenient cons effects.
(2) Parallel processing overhead does not affect the processing time.
(3) Memory contention is reduced by dividing the structure memory into many banks and by uniformly distributing cons operations in each bank.
2 citations
01 Apr 1985
TL;DR: Insight gained by trials on CLIP4, which typically showed speed gains of 40%, points to window-based architectures implemented using look-up tables in primitive extraction for low data-rate visual communication.
Abstract: Consideration is given to the tradeoff between algorithmic complexity and processing speed in primitive extraction for low data-rate visual communication. Initial experiments with serially-implemented algorithms on an MC68000 processor indicated the need for a high degree of parallelism in order to meet the requirements of real-time, moving-picture data rates. However, insight gained by trials on CLIP4, which typically showed speed gains of 40%, points to window-based architectures implemented using look-up tables.
1 citations