Degree of parallelism

About: Degree of parallelism is a research topic. Over the lifetime, 1515 publications have been published within this topic receiving 25546 citations.

The real-time implementation of a model-based measurement technique on a multiprocessor instrument

Abstract: This paper deals with the application of a high-performance instrument which embodies a multiprocessor network and a special data acquisition board Specifically it has been adopted for the real-time implementation of a model-based measurement technique, based on a parallel solution of a measurement algorithm derived from a dynamic mathematical model of the system under analysis The research reported in this paper has been oriented toward a real application We have tested the performance of our implementation, carrying out measurement of quantities which cannot be directly sensed on linear induction motors The results obtained by using this instrument are discussed, showing the system performance in terms of execution speed The effective errors of the acquisition system have been examined, in order to estimate the achievable accuracy, highlighting the influence of the ADC bit number on the measured quantities Furthermore the truncation error, which arises from the consideration of only a finite number of current harmonics, has been evaluated Finally the implementation of the measurement algorithm on a different number of processors has made it possible to evaluate its degree of parallelism by measuring the different speed-up factors

Uniform design of parallel programs for DSP

Abstract: It is shown that there is a close relationship between the mappings of sequentially formulated algorithms onto different kinds of parallel architectures. The compilation of programs for these architectures shares common optimization features, such as a high degree of parallelism, a short execution time, and a high processor utilization, and also a common design trajectory. Given a problem formulation, parallelism is extracted. Equivalence transformations are applied for the purpose of optimization. In the mapping phase, resources are assigned to operations and a schedule is defined. In order to match a problem and an architecture of given size, hierarchical transformations are performed that partition a problem into problems of smaller size that are executed sequentially. Due to these similarities, design methods known for the design and optimization of processor arrays can be used to solve problems known from the design of vectorizing compilers for supercomputers and vice versa. For defining the tasks of a versatile compiler for massive parallel architectures (COMPAR) a set of parameterized tools is defined that allows the uniformization of the mapping of sequential code onto parameterized parallel architectures. >

A Case Study of Accelerating Apache Spark with FPGA

Abstract: Apache Spark is an efficient distributed computing framework for big data processing. It supports in-memory computation of RDDs (Resilient Distributed Dataset) and provides a provision of reusability, fault tolerance, and real-time stream processing. However, the tasks in Spark framework are only performed on CPU. The low degree of parallelism and power inefficiency of CPU may restrict the performance and scalability of the cluster. In order to improve the performance and power dissipation of the data center, heterogeneous accelerators such as FPGA, GPU, MIC (Many Integrated Core) exhibit more efficient performance than the general-purpose processor in big data processing. In this work, we propose a framework to integrate FPGA accelerator into a Spark cluster. We use FPGA to accelerate the Spark tasks developed with Python, and in this way, the main computing load is performed on FPGA instead of CPU. We illustrate the performance of the FPGA based Spark framework with a case study of 2D-FFT algorithm acceleration. The results showed that FPGA based Spark implementation acquires 1.79x speedup than CPU implementation.

A decentralized virtual memory scheme implemented on an emulated multiprocessor

Abstract: A decentralized scheme for virtual memory management on MIMD (multiple-instruction-multiple-data) multiprocessors with shared memory has been developed Control and data structures are kept local to the processing elements (PE), which reduces the global traffic and makes a high degree of parallelism possible Each of the PEs in the target architecture consists of a processor and part of the shared memory and is connected to the others by a common bus The traditional approach, based on replication or sharing of data structures is not suitable in this case when the number of PEs is of the magnitude of 100 This is due to the excessive global traffic caused by consistency or mutual exclusion protocols A variant of the Dennings working set page replacement algorithm is used, in which each process owns a page list Shared pages are not present in more than one list, and it is shown that this will not increase the page fault rate in most cases >