Topic
Degree of parallelism
About: Degree of parallelism is a research topic. Over the lifetime, 1515 publications have been published within this topic receiving 25546 citations.
Papers published on a yearly basis
Papers
More filters
Patent•
28 Mar 2007
TL;DR: In this article, the same operation among the prediction formulas in 17 different prediction modes of 4x4 block with 16 pixels adopting digit computation strength cut method to remove computation redundancy, which can process the predicted values of 16 pixels within every clock cycle.
Abstract: The invention belongs to Video decoder IC design field. The character is in that: to the same operation among the prediction formulas in 17 different prediction modes of 4x4 block with 16 pixels adopting digit computation strength cut method to remove computation redundance; providing a in-frame predictor system with high degree of parallelism, which can process the predicted values of 16 pixels within every clock cycle. From the results achieved, compared to the design with the use of reconstruction, this invention can decrease circuit area under same parallelism and simplifies the control logic.
3 citations
04 Aug 1999
TL;DR: An extended list-scheduling algorithm is proposed which uses the above number of required registers as a guide to derive a schedule for G that uses as few registers as possible and, based on such an algorithm, an integrated approach for register allocation and instruction scheduling for modern superscalar architectures can be developed.
Abstract: Modern superscalar architectures with dynamic scheduling and register renaming capabilities have introduced subtle but important changes into the tradeoffs between compile-time register allocation and instruction scheduling. In particular, it is perhaps not wise to increase the degree of parallelism of the static instruction schedule at the expense of excessive register pressure which may result in additional spill code. To the contrary, it may even be beneficial to reduce the register pressure at the expense of constraining the degree of parallelism of the static instruction schedule. This leads to the following interesting problem: given a data dependence graph (DDG) G, can we derive a schedule S for G that uses the least number of registers ?
In this paper, we present a heuristic approach to compute the near-optimal number of registers required for a DDG G (under all possible legal schedules). We propose an extended list-scheduling algorithm which uses the above number of required registers as a guide to derive a schedule for G that uses as few registers as possible. Based on such an algorithm, an integrated approach for register allocation and instruction scheduling for modern superscalar architectures can be developed.
3 citations
14 Aug 2011
TL;DR: The NP-hardness of this problem is proved and a polynomial special case is introduced and a branch and bound procedure for the general case is presented along with computational results interpretation demonstrating its practical relevance.
Abstract: This paper is devoted to the problem of estimating the achievable degree of parallelism for a parallel algorithm with respect to a bandwidth constraint. In a compiler chain for embedded parallel microprocessors such an estimation can be used to fix an appropriate target for parallelism reduction "tools". Informally, our problem consists in task ordering and memory management for an algorithm, so as to minimize the number of memory accesses. After a brief survey of the literature, we prove the NP-hardness of this problem and introduce a polynomial special case. We then present a branch and bound procedure for the general case along with computational results interpretation demonstrating its practical relevance.
3 citations
17 Oct 2005
TL;DR: Boolean Web-service automata for distributed Web services are introduced as a parallel model for interaction and interoperability between applications and the generality of BWA leads to high degree of parallelism and efficient composition among Web service applications.
Abstract: Boolean Web-service automata (BWA) for distributed Web services are introduced as a parallel model for interaction and interoperability between applications. Boolean automata are a generalization of nondeterministic automata. The generality of BWA leads to high degree of parallelism and efficient composition among Web service applications. We also consider two formalisms - (1) deterministic Web-service automata (DWA), a model supporting Web service composition, (2) conversation Web-service automata (CWA), a conversation model supporting Web service interaction. DWA and CWA complement BWA in conjunction with the composition and conversation operations.
3 citations
17 Sep 1992
TL;DR: This approach, based on a string-coding functional and neural network, to solving the longest common subsequences problem with a high degree of parallelism, in this approach the parameters related to the input strings are contained entirely in the linear term of the neural network energy function.
Abstract: Presented is an approach, based on a string-coding functional and neural network, to solving the longest common subsequences (LCS) problem with a high degree of parallelism. In this approach, the parameters related to the input strings are contained entirely in the linear term of the neural network energy function, and the quadratic term only has to do with constraints. It is not necessary to modify the internal parameters and the connection weight matrix with new input strings. The complexities of both the network computing and the hardware implementation are substantially reduced. >
3 citations