Degree of parallelism

About: Degree of parallelism is a research topic. Over the lifetime, 1515 publications have been published within this topic receiving 25546 citations.

Introduction of dosim predicate to Prolog

Abstract: This paper proposes a predicate nameddosim which provides a new function for parallel execution of logic programs. The parallelism achieved by this predicate is a simultaneous mapping operation such as bagof and setof predicates. However, the degree of parallelism can be easily decided by arranging the arguments of the dosim goal. The parallel processing system with dosim was realized on a tight-coupled multiprocessor machine. To control the degree of parallelism and reduce the amount of memory required for execution, we introduce the grouping method for the goals executed in parallel and some variations of the dosim predicate. The effectiveness of the proposed method is demonstrated by the results of the execution of several applications.

Towards automated design of multicomputer system for real-time applications (architecture, task division)

Abstract: With the recent advances in VLSI technology it has now become feasible to design and implement computer systems consisting of a large number of processors. The suitability of such systems for specific applications depends primarily upon how well the system architecture corresponds to the structure of the algorithm(s) to be implemented. This work aims at the development of a software tool for designing an application-oriented or application-driven inhomogeneous multicomputer system (MCS) by evaluating the performance of the candidate architectures with respect to the algorithmic requirements of the application (task). The structure and the run-time ordering (data dependency of subtasks) of the applications are modeled by computation flow graphs (CFGs). The operating environments of the various MCSs have been represented by computing resource graphs (CRGs). CFG represents the degree of parallelism present in the task and the amount of computation and communication at each of its subtasks. Real-time applications in which continuous streams of input data are to be analyzed are considered in this work. An O(N('2)) time heuristic static allocation algorithm is presented to map the CFG to some CRG. The allocation algorithm provides a unique approach for reducing the interprocessor communication caused by the assignment of two communicating subtasks to different processors. This particular scheduling problem is shown to be NP-complete, and the heuristic algorithm presented in the thesis is shown to be bounded by a simple function of the number of levels in the CFG and the degree of inhomogeneity in the CRG. Performance of MCS for some application is evaluated in terms of speed-up, turn around time, resource utilization, and cardinality of the mapping, with the objective of evaluating an optimization function which could provide guidelines for selecting an architecture. The usefulness of the approach is demonstrated by comparing various MCSs for applications such as dynamic scene analysis problems, weather forecasting problems, fast fourier transforms, etc. The performance of the multicomputer systems for real-time applications is shown to be greatly influenced by its architecture. The software for the allocation algorithm and the simulation of MCS has been implemented on VAX 11/780 4.2 BSD UNIX using PASCAL and C. Finally, extensions of the project as a CAD tool and directions for the further research are outlined.

Optimising Skeletal-Stream Parallelism on a BSP Computer

Abstract: Stream parallelism allows parallel programs to exploit the potential of executing different parts of the computation on distinct input data items. Stream parallelism can also exploit the concurrent evaluation of the same function on different input items. These techniques are usually named "pipelining" and "farming out". The P3L language includes two stream parallel skeletons: the Pipe and the Farm constructors. The paper presents a methodology for efficient implementation of the P3L Pipe and Farm on a BSP computer. The methodology provides a set of analytical models to predict the constructors performance using the BSP cost model. Therefore a set of optimisation rules to decide the optimal degree of parallelism and the optimal size for input tasks (grain) are derived. A prototype has been validated on a Cluster of PC and on a Cray T3D computer.

Highly parallel space-time domain decomposition methods for parabolic problems

Abstract: In the past few years, the number of processor cores of top ranked supercomputers has increased drastically. It is challenging to design efficient parallel algorithms that offer such a high degree of parallelism, especially for certain time-dependent problems because of the sequential nature of “time”. To increase the degree of parallelization, some parallel-in-time algorithms have been developed. In this paper, we give an overview of some recently introduced parallel-in-time methods, and present in detail the class of space-time Schwarz methods, including the standard and the restricted versions, for solving parabolic partial differential equations. Some numerical experiments carried out on a parallel computer with a large number of processor cores for three-dimensional problems are given to show the parallel scalability of the methods. In the end of the paper, we provide a comparison of the parallel-in-time algorithms with a traditional algorithm that is parallelized only in space.

The VLSI High-Level Synthesis for Building Onboard Spacecraft Control Systems

Abstract: Using small spacecrafts for a wide range of research and applied purposes is one of the major trends in the aerospace field. Modular-network architectures implemented on the “system-on-chip” hardware platform provide required characteristics of onboard control systems. Selecting this system architecture significantly increases demands on very large-scale integration (VLSI) design efficiency and project solution quality. In this paper, we propose a new approach to VLSI high-level synthesis based on a functional-flow parallel computing model. The modified VLSI design flow uses a functional-flow parallel programming language Pythagoras, which allows describing a VLSI operation algorithm with the maximal degree of parallelism. An offered intermediate representation of VLSI architecture in the form of a control-flow graph and a data-flow graph provides an opportunity for synthesizing circuits and verifying projects on the stage of a formal description, without returning to previous hierarchical levels of the project. A set of software tools supporting new design process is developed. The proposed technology is successfully tested on the example of a digital signal processing function. Further, this technology is suggested for use in the synthesis of onboard control system components for small spacecrafts.