Topic
Degree of parallelism
About: Degree of parallelism is a research topic. Over the lifetime, 1515 publications have been published within this topic receiving 25546 citations.
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07 Oct 2010
TL;DR: A new Context-Adaptive Variable-Length Coding encoder is proposed particularly aimed to be implemented with Field Programmable Logics, capable to process 1080p@30 HDTV video streams coded in YCbCr 4:2:0, when it is implemented with a low-cost, low-speed FPGA.
Abstract: In this paper a new Context-Adaptive Variable-Length Coding encoder is proposed particularly aimed to be implemented with Field Programmable Logics. The design employs redundant circuitry to implement priority cascading logics which allows to highly improve its degree of parallelism, while the area cost related to the unavoidable replication of logic blocks has been balanced by means of arithmetic manipulations capable to eliminate some of the most area demanding tables of variable-length codewords. The proposed design is capable to process 1080p@30 HDTV video streams coded in YCbCr 4:2:0, when it is implemented with a low-cost, low-speed FPGA.
20 citations
01 Jan 1993
TL;DR: This paper presents a survey of high-performance switch fabric architectures which incorporate fast packet switching as their underlying switching technique to handle various traffic types.
Abstract: The rapid evolution in the field of telecommunications has led to the emergence of new switching technologies to support a variety of communication services with a wide range of transmission rates in a common, unified integrated services network. At the same time, the progress in the field of VSLI technology has brought up new design principles of high-performance, high-capacity switching fabrics to be used in the integrated networks of the future. Most of the recent proposals for such high-performance switching fabrics have been based on a principle known as fast packet switching. This principle employs a high degree of parallelism, distributed control, and routing performed at the hardware level. In this paper, we present a survey of high-performance switch fabric architectures which incorporate fast packet switching as their underlying switching technique to handle various traffic types. Our intention is to give a descriptive overview of the major activities in this rapidly evolving field of telecommunications.
20 citations
TL;DR: The proposed level based autonomic Workflow-and-Platform Aware (WPA) task clustering technique aims to achieve maximum possible parallelism among the tasks at a level of a workflow while minimizing the system overheads and resource wastage.
20 citations
TL;DR: The method improves the accuracy of previously developed decoupled schemes and preserves the accuracy and bandwidth properties of fully coupled compact schemes, even for a very large degree of parallelism, and enables the Navier‐Stokes equations to be solved independently on each processor.
Abstract: An improved domain‐decoupled compact scheme for first and second spatial derivatives is proposed for domain‐decomposition‐based parallel computational fluid dynamics. The method improves the accuracy of previously developed decoupled schemes and preserves the accuracy and bandwidth properties of fully coupled compact schemes, even for a very large degree of parallelism, and enables the Navier‐Stokes equations to be solved independently on each processor. The scheme is analysed using Fourier analysis and error analysis, and tested on one‐dimensional wave‐packet propagation, a two‐dimensional vortex convection problem, and in the direct numerical simulation of the three‐dimensional Taylor‐Green vortex problem and turbulent channel flow. Our results demonstrate the scheme's effectiveness in performing direct numerical simulation of turbulence in terms of accuracy and scalability.
20 citations
TL;DR: An architectural framework for parallel time-recursive computation is established and it is shown that the structure of the realization of a given linear operator is dictated by the decomposition of the latter with respect to proper basis functions.
Abstract: The time-recursive computation has been proven a particularly useful tool in real-time data compression, in transform domain adaptive filtering, and in spectrum analysis. Unlike the FFT-based ones, the time-recursive architectures require only local communication. Also, they are modular and regular, thus they are very appropriate for VLSI implementation and they allow a high degree of parallelism. In this two-part paper, we establish an architectural framework for parallel time-recursive computation. We consider a class of linear operators that consists of the discrete time, time invariant, compactly supported, but otherwise arbitrary kernel functions. We show that the structure of the realization of a given linear operator is dictated by the decomposition of the latter with respect to proper basis functions. An optimal way for carrying out this decomposition is demonstrated. The parametric forms of the basis functions are identified and their properties pertinent to the architecture design are studied. A library of architectural building modules capable of realizing these functions is developed. An analysis of the implementation complexity for the aforementioned modules is conducted. Based on this framework, the time-recursive architecture of a given linear operator can be derived in a systematic routine way.
20 citations