Degree of parallelism

About: Degree of parallelism is a research topic. Over the lifetime, 1515 publications have been published within this topic receiving 25546 citations.

An area reduced design of the Context-Adaptive Variable-Length encoder suitable for embedded systems

Abstract: In this paper a new Context-Adaptive Variable Length Coding (CAVLC) encoder architecture is proposed aimed to be implemented in embedded systems and field programmable logic. The design proposes novel Arithmetic Table Elimination (ATE) techniques, along with a table compression technique applied to those tables that cannot be eliminated by arithmetic manipulations. These approaches allows to halve the total number of tables requested by CAVLC algorithm and bring to an overall memory saving of about 87% with respect to an unoptimized implementation of the tables. Computational performances of the encoder have been improved by increasing the degree of parallelism through the use of priority cascading logic. With the proposed approaches the CAVLC encoder is capable of real time compression of 1080p HDTV video streams, coded in YCbCr 4:2:0, when it is implemented with a low-end Xilinx Spartan 3 FPGA, where the encoder achieves an operation frequency of 63MHz and requires an area occupancy of 2200 LUTs.

A Novel Algorithm for Online Inexact String Matching and its FPGA Implementation

Abstract: Among the basic cognitive skills of the biological brain in humans and other mammals, a fundamental one is the ability to recognize inexact patterns in a sequence of objects or events. Accelerating inexact string matching procedures is of utmost importance when dealing with practical applications where huge amounts of data must be processed in real time, as usual in bioinformatics or cybersecurity. Inexact matching procedures can yield multiple shadow hits, which must be filtered, according to some criterion, to obtain a concise and meaningful list of occurrences. The filtering procedures are often computationally demanding and are performed offline in a post-processing phase. This paper introduces a novel algorithm for online approximate string matching (OASM) able to filter shadow hits on the fly, according to general purpose priority rules that greedily assign priorities to overlapping hits. A field-programmable gate array (FPGA) hardware implementation of OASM is proposed and compared with a serial software version. Even when implemented on entry-level FPGAs, the proposed procedure can reach a high degree of parallelism and superior performance in time compared to the software implementation, while keeping low the usage of logic elements. This makes the developed architecture very competitive in terms of both performance and cost of the overall computing system.

Three-dimensional data stochastic transformation algorithms for hybrid supercomputer implementation

Abstract: This paper describes new three-dimensional algorithms of stochastic data transformation, offering a solution for information security problems The most important feature of these algorithms is a high degree of parallelism at the level of elementary operations In this paper we present a new 3D stochastic transformation called DOZEN, inspired by AES cipher, and two new constructions of S-box, called 2D and 3D S-boxes respectively

Parallel processsing in finite flement structural analysis

Abstract: A brief review is made of the fundamental concepts and basic issues of parallel processing. Discussion focuses on mechanisms for parallel processing, construction and implementation of parallel numerical algorithms, performance evaluation of parallel processing machines and numerical algorithms, and parallelism in finite element computations. A novel partitioning strategy is outlined for maximizing the degree of parallelism on computers with a small number of powerful processors.