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Degree of parallelism

About: Degree of parallelism is a research topic. Over the lifetime, 1515 publications have been published within this topic receiving 25546 citations.


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Proceedings Article
01 Jan 2008
TL;DR: The effects of increasing the number of items displayed to users in menus through parallelism are examined and it is found that moving from serial to a partially parallel (traditional) menu significantly improved user performance, but moving from a partially Parallel to a fully parallel menu design had more ambiguous results.
Abstract: Menus and toolbars are the primary controls for issuing commands in modern interfaces. As software systems continue to support increasingly large command sets, the user's task of locating the desired command control is progressively time consuming. Many factors influence a user's ability to visually search for and select a target in a set of menus or toolbars, one of which is the degree of parallelism in the display arrangement. A fully parallel layout will show all commands at once, allowing the user to visually scan all items without needing to manipulate the interface, but there is a risk that this will harm performance due to excessive visual clutter. At the other extreme, a fully serial display minimises visual clutter by displaying only one item at a time, but separate interface manipulations are necessary to display each item. This paper examines the effects of increasing the number of items displayed to users in menus through parallelism---displaying multiple menus simultaneously, spanning both horizontally and vertically---and compares it to traditional menus and pure serial display menus. We found that moving from serial to a partially parallel (traditional) menu significantly improved user performance, but moving from a partially parallel to a fully parallel menu design had more ambiguous results. The results have direct design implications for the layout of command interfaces.

11 citations

Proceedings ArticleDOI
17 Dec 2012
TL;DR: This work proposed a methodology that can adaptively adjust the thread-level parallelism in mapping a NPDP problem onto the GPU, thus providing sufficient and steady degrees of parallelism across different compute stages, and realizes the optimal matrix parenthesization problem.
Abstract: Our previous study focused on accelerating an important category of DP problems, called nonserial polyadic dynamic programming (NPDP), on a graphics processing unit (GPU). In NPDP applications, the degree of parallelism varies significantly in different stages of computation, making it difficult to fully utilize the compute power of hundreds of pro-cessing cores in a GPU. To address this challenge, we proposed a methodology that can adaptively adjust the thread-level parallelism in mapping a NPDP problem onto the GPU, thus providing sufficient and steady degrees of parallelism across different compute stages. This work aims at further improving the performance of NPDP problems. Sub problems and data are tiled to make it possible to fit small data regions into shared memory and reuse the buffered data for each tile of sub problems, thus reducing the amount of global memory access. However, we found invoking the same kernel many times, due to data consistency enforcement across different stages, makes it impossible to reuse the tiled data in shared memory after the kernel is invoked again. Fortunately, the inter-block synchronization technique allows us to invoke the kernel exactly one time with the restriction that the maximum number of blocks is equal to the total number of streaming multiprocessors. In addition to data reuse, invoking the kernel only one time also enables us to prefetch data to shared memory across inter-block synchronization point, which improves the performance more than data reuse. We realize our approach in a real-world NPDP application â" the optimal matrix parenthesization problem. Experimental results demonstrate invoking a kernel only one time cannot guarantee performance improvement unless we also reuse and prefetch data across barrier synchronization points.

11 citations

Journal ArticleDOI
06 Apr 2014
TL;DR: A research prototype is presented that uses a lightweight runtime environment to manage the resource-specific workloads, and to control the dataflow and parallel execution in hybrid systems, and is aptly capable of full utilization of a wide range of accelerator hardware.
Abstract: Hardware heterogeneity of the HPC platforms is no longer considered unusual but instead have become the most viable way forward towards Exascale. In fact, the multitude of the heterogeneous resources available to modern computers are designed for different workloads and their efficient use is closely aligned with the specialized role envisaged by their design. Commonly in order to efficiently use such GPU resources, the workload in question must have a much greater degree of parallelism than workloads often associated with multicore processors CPUs. Available GPU variants differ in their internal architecture and, as a result, are capable of handling workloads of varying degrees of complexity and a range of computational patterns. This vast array of applicable workloads will likely lead to an ever accelerated mixing of multicore-CPUs and GPUs in multi-user environments with the ultimate goal of offering adequate computing facilities for a wide range of scientific and technical workloads. In the following paper, we present a research prototype that uses a lightweight runtime environment to manage the resource-specific workloads, and to control the dataflow and parallel execution in hybrid systems. Our lightweight runtime environment uses task superscalar concepts to enable the developer to write serial code while providing parallel execution. This concept is reminiscent of dataflow and systolic architectures in its conceptualization of a workload as a set of side-effect-free tasks that pass data items whenever the associated work assignment have been completed. Additionally, our task abstractions and their parametrization enable uniformity in the algorithmic development across all the heterogeneous resources without sacrificing precious compute cycles. We include performance results for dense linear algebra functions which demonstrate the practicality and effectiveness of our approach that is aptly capable of full utilization of a wide range of accelerator hardware.

11 citations

Journal ArticleDOI
TL;DR: A new parallel computing solution of problems of coupled flows in soils is presented and an attempt is made to exploit a high degree of parallelism based on the use of a finite difference solution method.
Abstract: A new parallel computing solution of problems of coupled flows in soils is presented. Such phenomena occur when more than one transport process exists below ground as is the case, for example, for coupled chemical, electrical, heat, or moisture flow. A numerical solution of the governing differential equations is achieved via a new parallel computing algorithm, programmed using new parallel software and operated on new parallel hardware. An attempt is made to exploit a high degree of parallelism based on the use of a finite difference solution method. The specific problem considered in detail in the paper, as an example of one particular case that may be addressed, is that of coupled heat and moisture transfer in unsaturated soil. The validity of the results achieved are first discussed in relation to physically observed behavior. Qualitatively and quantitatively correct results are shown to have been obtained. The performance of the approach as an efficient parallel computing solution is then assessed. T...

11 citations

Journal ArticleDOI
TL;DR: In this article, a simple matrix formula for the distance between two flats or affine spaces of R n is derived and the geometry of intersection and degree of parallelism of two flats is elucidated.

11 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20221
202147
202048
201952
201870
201775