Delta-sigma modulation

About: Delta-sigma modulation is a research topic. Over the lifetime, 9077 publications have been published within this topic receiving 122322 citations.

Sigma-delta analog-to-digital converter capable of reducing idle tones while alternately conducting signal conversion and comparator offset calibration

Abstract: A sigma-delta analog-to-digital converter includes: a subtractor for subtracting a feedback signal from an analog input signal; a loop filter for processing the output signal from the subtractor to generate a filtered signal; a signal comparing circuit for selectively operating in an offset detection mode or a signal comparison mode, wherein the signal comparing circuit generates an error signal irrelevant to the relative magnitude between the filtered signal and a reference signal in the offset detection mode, and generates a comparison signal corresponding to the relative magnitude between the filtered signal and the reference signal in the signal comparison mode; an offset calibration control circuit for calibrating the offset of the signal comparing circuit and for controlling the signal comparing circuit to alternately switch between the offset detection mode and the signal comparison mode; and a digital-to-analog converter for generating the feedback signal according to the comparison signal.

Digital input signal processing method for digital delta-sigma modulator, involves generating filtered signal according to redundant arithmetic coding, generating output signal sampled on bits, and anticipating generation of output signal

Abstract: The method involves generating a filtered sampled signal (SF) according to a redundant arithmetic coding e.g. borrow-save coding. An output signal (Y) sampled on n bits is generated by using non-exact quantization. The generation of the output signal is anticipated, where the generation of the output signal is parallely carried out at the final elementary processing of the generation of the filtered sampled signal. An independent claim is also included for a digital delta-sigma modulator comprising a digital filtering unit.

Comparison of Simulation Methods of Single and Multi-Bit Continuous Time Sigma Delta Modulators

Abstract: .................................................................................................iii ACKNOWLEDGEMENTS...............................................................................iv TABLE OF CONTENTS...................................................................................v LIST OF TABLES..........................................................................................vii LIST OF FIGURES..........................................................................................x Chapter

Wideband Quadrature Sigma-Delta A/D Conversion for Cognitive Radio - Reconfigurable Design and Digital Mirror-Frequency Suppression

Abstract: This article proposes a reconfigurable wideband transfer function design for quadrature ΣΔ A/D converters combined with digital post-compensation of frequency-selective mirror-frequency interference (MFI) induced by the inherent mismatches between the in-phase (I) and quadrature (Q) rails of the receiver. When receiving wideband waveforms, e.g., similar to LTE signals, it is crucial for the compensation performance to be able to consider also frequency variations in the image rejection. In addition to compensating the MFI originating from inside the quadrature ΣΔ modulator (QΣΔM), the digital compensation considers also the interference generated at the preceding receiver front-end components, such as an I/Q mixer. The performance of this approach is illustrated with a 20 MHz reception bandwidth, being a practical example of requirements for modern communications waveforms. This concrete example is given with a two-stage QΣΔM giving eighth order noise-shaping.

Expediting analog design retargeting by design knowledge re-use and circuit synthesis: a practical example on a Delta-Sigma modulator

Abstract: In the past decade or two, due to constant and rapid technology changes, analog design re-use or design retargeting to newer technologies has been brought to the table in order to expedite the design process and improve time-to-market. If properly conducted, analog design retargeting could significantly cut down design cycle compared to designs starting from the scratch. In this article, we present an empirical and general method for efficient analog design retargeting by design knowledge re-use and circuit synthesis (CS). The method first identifies circuit blocks that compose the source system and extracts the performance parameter specifications of each circuit block. Then, for each circuit block, it scales the values of design variables (DV) from the source design to derive an initial design in the target technology. Depending on the performance of this initial target design, a design space is defined for synthesis. Subsequently, each circuit block is automatically synthesised using state-of-a...