Showing papers on "Depletion region published in 1973"

Photocapacitance Studies of the Oxygen Donor in GaP. I. Optical Cross Sections, Energy Levels, and Concentration

Abstract: Photocapacitance studies in GaP $p\ensuremath{-}n$ junctions have given new insight to the deep states associated with the O donor. In addition to the well-known neutral state in which O binds an electron by 0.9 eV, a new state in which O deeply binds a second electron was discovered. The second electron is captured into a level \ensuremath{\sim} 0.45 eV deep, after which lattice relaxation increases the average optical-ionization energy to \ensuremath{\sim} 2.0 eV. The role of lattice relaxation was established by studying the temperature dependence of the photoionization of the trapped electrons. Profile measurements of the O-donor density through the depletion layer indicated a decrease in O-donor concentration from 1.5\ifmmode\times\else\texttimes\fi{}${10}^{16}$ on $p$ to 4\ifmmode\times\else\texttimes\fi{}${10}^{14}$ on the $n$ side. Optical cross sections and thermal-emission rates of both electrons were measured. Both electrons were stable below 100 \ifmmode^\circ\else\textdegree\fi{}C.

MOS threshold shifting by ion implantation

Abstract: In this paper, the theoretical description of threshold shifting of MOS devices by implantation of an impurity beneath the control electrode is presented. Experimental measurements are presented which verify the theoretical predictions. In particular, MOS capacitors and transistors were used to experimentally verify the theory ( n -type Si substrates to verify the case of p -channel devices). Implanted layers sufficient to compensate the background substrate doping were used. This layer creates a buried conducting channel beneath the gate that is isolated from the substrate by the p-n junction. Modulation of this conduction region by the surface depletion region was found to be responsible for the transistor action. For n -type substrates ( p -channel devices) ion energies of 33 and 53 keV were selected for use with gate oxides of ≈ 0·1 μm. Boron doses ranged from 5×10 10 to 2×10 12 atoms/cm 2 . Threshold shifts from 0·2 to 5 V were observed. Device performance was not degraded by the implantation. Annealing temperatures as low as 500°C were found to be sufficient to anneal the damage caused by the implantation. Changes in the characteristic C vs V curves of the devices were predicted and experimentally observed. A method of picking the approximate turn-off voltage of the devices from the C vs V curves is pointed out.

Low capacitance V groove MOS NOR gate and method of manufacture

Abstract: An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.

Proton-implanted optical waveguide detectors in GaAs

Abstract: Defect levels introduced by implanting GaAs with high-energy protons give rise to optical absorption at wavelengths greater than that of the normal absorption edge at 0.9 µ. Optical waveguide detectors may be fabricated by taking advantage of this absorption mechanism in the presence of a Schottky barrier depletion layer. Detector response times less than 200 ns and external quantum efficiencies of 16% have been observed.

High voltage, high frequency double diffused metal oxide semiconductor device

Abstract: High voltage, high frequency metal oxide semiconductor device having a precisely controlled channel extending to the surface and in which a metallization overlies a thick insulating layer and substantially covers the depletion region in the drain for breakdown voltage control.

The potential in a charge coupled device with no mobile minority carriers and zero plate separation

Abstract: A two-dimensional analysis of the potential in charge coupled devices is presented. It is assumed that there are no mobile minority carriers, that the plate separation is zero, and that the plate voltage does not vary with time. The depletion layer approximation is used to linearize the equations, which are then solved exactly with the use of Fourier series. Both surface and buried channel devices are analyzed. These solutions can typically be evaluated on a computer in less than a tenth of the time it takes to obtain a solution by the method of finite differences. The solutions obtained here provide an important tool for the designer of charge coupled devices. In addition to describing the method of obtaining the solutions, we evaluate them to show the effects of a number of different design parameters, and compare the cost of these solutions with the cost of obtaining finite difference solutions.

Double-drift IMPATT diodes near 100 GHz

Abstract: This paper reports the highest x power (frequency)2IMPATTS produced to date. A CW output power of 380 mW has been achieved at 92 GHz with an efficiency of 12.5 percent. An all-implanted double-drift n+-n-p-p+silicon structure was fabricated, using a lightly doped epitaxial layer as the starting material. The newly made structure uses a more shallow n+contact than previous diodes, and therefore has more equal drift spaces. Small-signal admittance calculations show lower susceptance per unit area in the newly made structure. The shallow contact has allowed the study of unequal dopings in the n- and p-drift spaces. Unequal dopings up to 50 percent can be tolerated with less than 20 percent variation in measured efficiency and output power. Both admittance and breakdown voltage calculations based upon experimentally determined doping profiles and independently measured ionization coefficients were found to be in good agreement with experiment. The doping profiles on both sides of the depletion region were determined by C(V) analysis. The testing of both the old and new structures has been carried out in a microwave circuit having improved mechanical tuning accuracy due to the introduction of a newly designed tuning plunger.

Bulk charge transfer semiconductor device

Abstract: In a charge transfer semiconductor device majority carriers are transferred within a semiconductor body on a substrate from means for introducing majority carriers to means for detecting transferred majority carriers by applying pulsed voltages to a series of electrodes disposed on an insulating layer which is disposed on one surface of the semiconductor body between the introducing means and the detecting means. Depletion regions are formed within the semiconductor body, so that one end of a depletion region below one electrode reaches the substrate and another end of a depletion region below an electrode next to the one electrode does not reach the substrate, whereby majority carriers below the one electrode are pushed out below the next electrode.

Depletion layer characteristics at the surface of beveled high-voltage P-N junctions

Abstract: The design of high-voltage p-n-junction devices used today is usually based on beveling of the p-n junctions in order to reduce the tangential surface field far enough below the bulk field and to secure thus that breakdown occurs in the bulk of the device rather than at the surface. Using relaxation methods, solutions of Poisson's equation in two dimensions have been found which reveal that for commonly used bevelings of the forward-blocking junction in a thyristor structure, the electric field in the region below the surface is larger than in the bulk and at the surface. This field is strongly dependent on surface charges. It is shown that bevelings avoid the surface breakdown but the body breakdown obtained is not the true bulk breakdown as expected but rather occurs in the immediate neighborhood to the surface. The calculations make it possible to obtain the breakdown voltage for beveled structures. Measurements of the tangential surface field obtained by probing the junctions, light-spot measurements of the space-charge-region width on the surface and capacitance measurements of the surface charge as well as breakdown measurements are in good agreement with the calculations. This approach has led to the design of high-voltage thyristor structures that exhibit true bulk breakdown and, at the same time, loss of semiconducting material due to beveling is reduced.

Exact frequency dependent complex admittance of the MOS diode including surface states, Shockley-Read-Hall (SRH) impurity effects, and low temperature dopant impurity response☆

Abstract: Solutions of prespecified accuracy for an a.c. transmission line model of the semiconductor in the MOS structure have been found. Together with an accurate solution of the d.c. bias problem, exact capacitance-voltage ( C - V ) and conductance-voltage ( G - V ) characteristics can be found at any frequency. Shockley-Read-Hall (SRH) centres and surface states have been included in both the d.c. and a.c. solutions. In addition, accurate low temperature dopant impurity response can be studied since the d.c. solution uses full Fermi integrals over arbitrary densities of states with the impurity dopant band treated like an SRH centre for the a.c. solution. In terms of such non equilibrium situations as occur with the application of light or carrier injection by tunneling, the a.c. solution requires active elements in the transmission line model but the transmission line can still be solved to a prespecified accuracy provided an accurate solution of the d.c. bias problem can be found. In this paper the d.c. solution for the case of light induced pair production was done under the assumption of bulk controlled d.c. quasi Fermi level shifts and thus the accuracy of the related a.c. conductance and capacitance solutions is dependent on the reliability of this assumption. The theoretical studies of parameter effects now possible over the complete frequency, temperature, and d.c. bias ranges allow quantitive prediction of most MOS electrical measurements. It is hoped that this will enable MOS experiments to be used more effectively in determination of space charge region phenomena as well as improving interface characterization.

Method and apparatus for storing and transferring information

Abstract: A method and apparatus for storing and transferring information employing a conductor-insulator-semiconductor (CIS) structure as the storage and transfer apparatus is disclosed herein. The CIS structure is initially charged to a predetermined voltage thereby forming a depletion region within the semiconductor beneath the insulated conductor. Minority carriers controllably generated within the semiconductor are stored at the surface of the semiconductor beneath the insulated conductor by an electric field existing in the depletion region, thus changing the predetermined voltage. Means for transferring the stored charge along the surface of the semiconductor are disclosed.

Impact ionization current in MOS devices

Abstract: An impact ionization current flows in the substrate of an MOS device which is operated in the saturation region This current results from hole-electron pairs created by impact ionization in the drain depletion region This paper utilizes the transverse electric field across the depletion region and the probability of creating a hole-electron pair as a function of this field to calculate substrate current which is then compared with measured data

The calculation of the avalanche multiplication factor in silicon p—N junctions taking into account the carrier generation (thermal or optical) in the space-charge region

Abstract: The influence of carrier generation within the space-charge regions of silicon p-n junctions upon their breakdown characteristics is analyzed. Universal plots for the calculation of the total multiplication in one-sided silicon junctions versus voltage and substrate concentration are given, which take into account both injection and generation of initiating carriers. It is shown that the multiplication factor M of practical (i.e., generation-dominated) silicon junctions differs from the pure hole-pure electron multiplication factors M p and M n and ranges between them, i.e., M_{p} . Its calculated voltage dependence is well approximated by Miller's relationship with an exponent n between 4 and 7 for impurity concentrations in the substrate between 1014and 1017cm-3.

Semiconductor capacitor structure and memory cell, and method of making

Abstract: In one example, a random access memory cell includes an MOS gating transistor to activate the cell for reading, writing, or refreshing data stored on a cell capacitor structure. A typical cell transistor includes P1 (input/output) and P2 (cell storage) diffusions in an N-type substrate, P2 serving as one terminal or plate of the cell capacitor structure. According to this application, a preferred cell capacitor is formed by diffusing an N+ region over a major portion of the P2 region and extending beyond the P2 region in electrical contact with the grounded N substrate. The primary cell capacitor is defined between the P2 diffusion, a depletion region induced at the P2-N+ junction when P2 is charged, and the grounded N substrate. The N+ diffusion also reduces an unwanted parasitic capacitance between the P2 region and a transistor gate conductor for the cell, reduces leakage currents and permits greater packing density of cells. More generally, the application relates to an improved semiconductor capacitor storage structure and method, including a substrate of one conductivity type, a first diffusion of the opposite type on the substrate and constituting one capacitor terminal, and a second diffusion of the substrate conductivity type covering most of the first diffusion and in electrical contact with the substrate, the second diffusion and substrate forming the second capacitor terminal. The dielectric of the capacitor storage structure is formed by a depletion region between the first diffusion and both the substrate and second diffusion.

Method of making a planar graded channel MOS transistor

Abstract: The method of fabrication of a planar narrow channel metal oxide semiconductor field effect transistor (MOSFET) by a double diffusion through a self-aligned silicon gate wherein a first type dopant is diffused into the same self-aligned window of the source diffusion already diffused with a second type dopant. The diffused source and drains are self-aligned by means of the silicon gate, thus permitting narrow gate lengths. The diffusion profile is such that the impurity concentration near the source is higher than that near the drain. When a reverse bias is applied between, for example, an n-type drain and a p-type diffused region, the depletion layer cannot widen as much toward the source as a uniform channel because of the impurity concentration profile. Thus a narrow channel length can be used withoout drain-source punch-through at low voltages. Meanwhile, the self-aligned silicon gate permits a close spacing between the source and drain contacts, thus reducing the feedback capacitance between the drain and the gate.

An experimental determination of the carrier lifetime near the SiSiO2 interface

Abstract: Leakage currents in phosphorus-gettered (111) silicon have been studied at room temperature using a MOS gate-controlled diode structure The leakage current and the gate-substrate capacitance have each been measured as a function of gate voltage for different values of reverse bias From these measurements the carrier lifetime in the depletion region near the SiSiO2 interface has been deduced It is found that the lifetime decreases with distance from the interface; an explanation for this is suggested

Information Management System: The potential in a charge-coupled device with no mobile minority carriers

Abstract: The potentials and fields in a two-dimensional model of a charge-coupled device (CCD) are studied. We assume no mobile minority carriers have been injected into the CCD and that the electrode voltages do not vary with time. The nonlinear equations describing the devices are first linearized using the depletion layer approximation. The linearized equations are then solved approximately by a fitting technique. Both surface and buried channel CCD's are considered. The accuracy and cost of obtaining the solution is discussed. This work is a continuation of a study initiated in an earlier paper.1

Oriented polycrystal jfet

Abstract: A junction field effect transistor in which the source and drain electrodes are connected by a large number of exceedingly slender rod-shaped semiconductor crystals grown side by side parallel to each other and each having an outer sheath of opposite conductivity semiconductor material. Each crystal and its sheath have a P-N junction between them and all of the sheaths are connected together to a gate terminal. Application of a gate voltage to this terminal causes a depletion layer within each rod-shaped crystal to constrict the charge-carrying path through the crystal to an extent determined by the magnitude of the gate voltage. The rod-shaped crystals are grown in such a way that individual rod-shaped crystals are formed rather than a single crystal of large area.

Device for storing information and providing an electric readout from a conductor-insulator-semiconductor structure

Abstract: An information storing method and a storing device using a conductor-insulator-semiconductor (CIS) structure as the storage element is disclosed within. The CIS structure is initially charged to a predetermined voltage, forming a depletion region within the semiconductor beneath the conductor. Minority carriers are controllably generated within the semiconductor in proportional response to an information-bearing signal such as a specific amount of electromagnetic radiation flux. The generated minority carriers move to and are stored at the surface of the semiconductor beneath the conductor due to the electric field existing in the depletion region, thus changing the predetermined voltage. The change in voltage which may be determined is a measure of the number of generated minority carriers and, therefore, is a measure of the integrated electromagnetic radiation flux and constitutes the stored information.

On the validity of the gradual channel approximation for junction field effect transistors with drift velocity saturation

Abstract: The errors are analyzed which result from the gradual channel approximation for junction field effect transistors with drift velocity saturation of carriers Near the drain the neglect of the second derivative of potential with respect to position coordinate along the channel in Poisson's equation for the depletion layer is found to be more stringent than that of the field component normal to the channel boundary The resulting errors are presented as a function of a dimensionless parameter which is proportional to mobility and pinch-off voltage and inversely proportional to channel length and saturation drift velocity A modified channel boundary is constructed at which the boundary condition is exactly satisfied

Threshold adjustment of N-channel enhancement mode FETs by ion implantation

Abstract: Ion implantation of11B+directly into the channel region was used to adjust the threshold voltage of n-channel enhancement mode FETs. Implantation was performed through a 500A gate oxide grown during a standard four-mask FET process. Threshold voltage shift was determined as a function of implant dose and energy by measuring the difference in threshold voltage between implanted and unimplanted devices on the same wafer. Threshold voltage shift varied sublinearly with implant dose. These are believed to be the first results reported accurate enough to show this effect. Threshold voltage shift for a given dose is also reduced as implant energy (or channel depth) is increased. These results are easily understood in terms of a simple model in which the collapse of the depletion region at inversion, due to the additional doping in the channel, partially compensates for this additional doping. Data are compared with a numerical solution that for the first time fully accounts for the nonuniform doping profile, with excellent agreement.

Magnetic field dependent field effect transistor

Abstract: A magnetic field effect transistor comprises a semiconductor body with a region of a specific type of conductivity, a source and a drain electrode between which is provided a channel region formed by a narrowed part of the region of the specific type of conductivity at least one barrier layer defining the channel region and controlling the channel region through the space charge region issuing from the barrier layer, and at least one additional electrode positioned laterally of the direct charge carrier path between the source and drain electrodes and to which at least part of the charge carrier can be deflected in the presence of a suitable magnetic field

Magnetic field dependent field effect transistor

Abstract: A magnetic field effect transistor comprises a semiconductor body with a region of a specific type of conductivity, a source and a drain electrode between which is provided a channel region formed by a narrowed part of the region of the specific type of conductivity at least one barrier layer defining the channel region and controlling the channel region through the space charge region issuing from the barrier layer, and at least one additional electrode positioned laterally of the direct charge carrier path between the source and drain electrodes and to which at least part of the charge carrier can be deflected in the presence of a suitable magnetic field.

High voltage bipolar semiconductor device and integrated circuit using the same and method

Abstract: Planar bipolar semiconductor device in which a substantial portion of the collector base junction is covered by an insulating layer and has a layer of metallization overlying a substantial portion of the collector region to cause the depletion layer to be moved into the bulk of the semiconductor body and to be spread over a large area whereby the electric field is greatly reduced to cause breakdown to take place within the semiconductor body rather than at the surface. In an integrated circuit, the bipolar device is isolated by the use of dielectric isolation.