Showing papers on "Depletion region published in 1983"

Low field mobility of 2‐d electron gas in modulation doped AlxGa1−xAs/GaAs layers

Abstract: We derive a simple analytical formula for the low field electron mobility which uses the 2‐d degenerate statistics of the 2‐d electron gas. This takes into account the finite width of the depletion layer in (Al,Ga)As for the scattering by remote donors, scattering by the interface charge, and the polar‐optical and acoustic deformation potential and piezoelectric scattering. The largest measured value of mobility is determined by scattering due to interface charge in some cases. The ultimate value of the mobility which may be achieved is limited by the acoustic deformation potential and piezoelectric scattering at about 6.5×106 cm2/V s for an interface carrier density of the 2‐d electron gas ns0 ≂4×1011 cm−2. Our results agree very well with experimental data obtained in our laboratory as well as other laboratories.

Collection of charge from alpha-particle tracks in silicon devices

Abstract: Experimentally and by computer simulation, we have investigated the collection process of alpha-particle-generated charge in silicon devices. We studied the total charge collected and the transient characteristics of collection for various structures. Analytic results indicate that a strong drift field extends far beyond the original depletion layer, and funnels a large number of carriers into the struck node. This field-funneling component of charge collection is a strong function of substrate resistivity and bias voltage. It is relatively independent of the area of the struck device. The collection is less efficient for a small capacitance node. The funneling also occurred with a time delay when an alpha particle missed the field region by a short distance. Devices on an n-type substrate were also studied. They exhibit a similar funneling effect as the p-type substrate. The agreement between measurement and simulation is excellent. The impact on future VLSI design is discussed.

A reevaluation of the meaning of capacitance plots for Schottky‐barrier‐type diodes

Abstract: Capacitance–voltage (C‐V) data, in the form of 1/C2 versus voltage plots, have long been used to extract information on the space charge region doping and barrier height in Schottky‐barrier‐type diodes. The meaning of the slope and voltage intercept of these 1/C2 versus voltage plots for reverse‐biased diodes is reexamined in this analysis for the case when there is an inadvertent or purposeful interface layer present. The possibility of having interface states, one type of which communicates with the metal and another type of which communicates with the semiconductor, is considered, as is the fact that these two classes of states may, or may not, be able to follow an ac signal. The analysis first assumes that the densities of these states do not vary across the gap; this restriction is later relaxed and the possibility of variable densities of interface states is considered. The results of the analysis differ from those of previous studies. In general, it is found that most sets of interface state charac...

Barrier layer for photovoltaic devices

Abstract: An improved semiconductor device, adapted to provide electrical current in response to light energy incident thereon, includes a first electrode, an active semiconductor body atop the first electrode, a second electrode atop the semiconductor body, and at least one defect region which is capable of providing a low resistance shunt path for the flow of electrical current between the electrodes of the device. The improvement comprises a continuous transparent barrier layer (1) operatively disposed between the semiconductor body and one of the electrodes of the device and (2) adapted to decrease the flow of electrical current through the at least one defect region of the semiconductor device. The barrier layer is formed from a material chosen from the group consisting essentially of oxides, nitride and carbides of: indium, tin, cadmium, zinc, antimony, silicon, chromium and mixtures thereof. Methods of (1) fabricating improved semiconductor devices and (2) preventing operational mode failures due to latent detents are also disclosed.

Discharge Kinetics of the Nickel Electrode

Abstract: The kinetics of nickel electrode discharge are found to be controlled by solid-state proton diffusion under normal high rate discharge conditions. As the nickel electrode is discharged, the conductivity of the active material decreases until eventually mixed kinetics are observed where the electrode impedance has significant contributions from both proton diffusion and charge transfer resistance. Further discharge results in the formation of a semiconductor layer at the metal-active material interface that is depleted in charge carriers and has a relatively high electronic resistance. The depletion layer is responsible for the secondary discharge plateau of the nickel electrode at 0.0 to -0.5 V vs. Hg/HgO. Changes in electrode capacitance during depletion layer formation appear to provide a sensitive measure of the uniformity of electrode discharge. The effects of cobalt additives on the kinetics have been experimentally measured, and while cobalt does not change the discharge mechanism, it does increase the ionic and electronic conductivity of the active material, allowing a greater depth of discharge before depletion layer formation.

Generation‐annealing kinetics and atomic models of a compensating donor in the surface space charge layer of oxidized silicon

Abstract: Experimental evidence of the generation of a shallow bulk donor center in the surface space‐charge layer of oxidized silicon by exposure to a high dose of 10‐keV electron is first summarized. An extensive new study of the generation and annealing kinetics of a similar bulk donor in p‐Si metal‐oxide‐semiconductor capacitors subjected to as much as 20 C/cm2 avalanche electron injection is then reported. The generation kinetics from 180 to 298 K is first order with a constant total donor concentration of about 1×1017 cm−3 which is independent of both injection temperature and voltage, and a generation cross section given by 8.6×10−18 exp(−113 meV/kT) cm2, which increases with injection voltage. Rapid annealing begins at 50 °C following a second‐order kinetics from 50 °C to 150 °C with an annealing rate given by 4.2×10−7 exp(−1.07 eV/kT) cm3/sec. Analyses of the results suggest that a bulk oxygen donor is the origin, and the bimolecular annealing kinetics involves hydrogen bonding of the oxygen donor dangling...

Analysis of the dark current and photoresponse of In0.53Ga0.47As/InP avalanche photodiodes

Abstract: The doping profiles, current-voltage (I–V) and photoresponse characteristics of five In0.53Ga0.47As/InP avalanche photodiode (APD) wafers are presented. A detailed analysis indicates that the dark current is due largely to generation and recombination of carriers in the diode bulk, and in some wafers tunneling at the p-n junction is dominant near breakdown (VB). In some cases, significant surface currents are also observed. In three high-performance wafers, however, low primary dark currents (∼5 nA) with no evidence for tunnelling at 0.99 VB have been obtained. In addition, microplasmas have been found in some wafers, due to local breakdown possibly arising from crystalline defects. Nevertheless, we report uniform gains as high as 100. The dark current and gain characteristics of these devices are among the best reported to date for In0.53Ga0.47As/InP APDs. Finally, the response of the APDs to fast optical pulses has been analyzed at both low and high illumination intensity. The slow speed of response, which has been reported elsewhere, is considered in detail and is found to be due to charge pile-up at the abrupt n-In0.53Ga0.47As/n-InP heterointerface which is characteristic of our devices. Using an analysis of the response time thermal activation energy along with the transient pulse shape, we infer that the heterointerfaces are graded over a length of 2 L ≌ 300 A . The model predicts that fast response can be obtained for heterointerface grading lengths of 2 L ⩾ 500 A , depending on the epitaxial layer doping and extent of penetration of the depletion region into the In0.53Ga0.47As layer at breakdown.

Influence of a Strong Electric Field on the Carrier Capture by Nonradiative Deep-Level Centers in GaAs

Abstract: The techniques of capacitance spectroscopy are used to measure directly electron and hole capture cross-sections of deep levels in a neutral material at zero electric field and in the depletion layer with a strong electric field. The data show that if at zero electric field the electron capture cross-sections onto the centers are thermally activated and described by the theory of nonradiative multiphonon capture, then in a strong electric field (F ≈ 104 V/cm) the capture cross-sections increase to the limiting large value (σ ≈ 10−14 to 10−12 cm2) and are only little dependent on temperature. It is shown that an electric field causes a simultaneous increase of the electron and hole capture cross-sections of the level EL2 by five orders of magnitude at low temperatures (T ≈ 90 K). [Russian Text Ignored]

Electrical measurements on n+‐GaAs‐undoped Ga0.6Al0.4 As‐n‐GaAs capacitors

Abstract: Current versus voltage (I‐V) and capacitance versus voltage (C‐V) characteristics have been measured for n+‐GaAs‐undoped Ga06Al04 As‐GaAs capacitors over a temperature range of 80–350 K At low temperatures the structure behaves like a semiconductor‐insulator‐semiconductor diode with interface barrier heights of 038 and 040 eV for the bottom and top interfaces, respectively The I‐V curves exhibit a rectifying behavior due to the formation of a substrate depletion layer, and the C‐V curves show the formation of the depletion layer under reverse bias as well as an accumulation layer containing >1012 electrons/cm2, in forward bias The C‐V curves agree closely with standard theory for SIS structures assuming Fermi–Dirac statistics for electrons in the accumulation layer, within an unaccounted‐for voltage shift of 016 V

Surface photovoltage measured capacitance: Application to semiconductor/electrolyte system

Abstract: Surface photovoltage measured capacitance (SPMC), a novel technique for determining the properties of semiconducting materials, is introduced. SPMC permits the determination of a semiconductor depletion layer capacitance by measuring changes of the surface potential barrier induced by low intensity chopped light whose photon energy exceeds the band‐gap energy. The theory of the SPMC technique is derived, and an equivalent circuit for analyzing the measurements is described. The present technique is compared with the conventional current measured capacitance method, and it is shown that using SPMC the separation of the depletion layer capacitance from the influence of the surface states can be performed by measurements at only one frequency of light modulation. This is a simpler procedure than the frequency dispersion measurement required of conventional capacitance techniques. Measurements of the capacitance‐voltage characteristics of a semiconductor/electrolyte system, in particular n‐type WS2 exposed to...

Semiconductor memory and method for fabricating the same

Abstract: A semiconductor memory is provided having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor. In particular, an arrangement is provided to prevent a depletion region formed around the groove from growing into an adjacent capacitor. By virtue of this, both the area occupied by each memory cell and the distance between the memory cells can be made very small. Accordingly, high density integration is facilitated.

Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique

Abstract: Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implemented junction extension for precise control of the depletion region charge in the junction termination. A theory is presented which shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, diodes with a normal breakdown voltage of 1050 V and a 0.5 mA leakage current become 1400 V (1450 ideal) devices with a 5 µA leakage current. Applications of the junction termination technique is feasible in MOS technology, but is more attractive in power devices where reduced surface fields are as important as the extremely high breakdown voltages. Reduced surface fields allow more flexibility in passivation techniques, two of which we have used to date. Our results also show that the implant can be activated at a variety of temperatures with a good degree of success; process flexibility being the goal of these tests.

Surface‐tunneling‐induced 1/ f noise in Hg1−xCdxTe photodiodes

Abstract: The reverse bias dark curent of Hg1−xCdxTe (MCT) photodiodes is often dominated by tunneling across a pinched off surface depletion region. The width of this critical region may be modulated by charge exchange with slow surface states in a passivant insulator. Numerical calculations give the correct order of magnitude for observed 1/ f noise in ZnS passivated MCT photodiodes.

Measurements of Alpha-Particle-Induced Charge in GaAs Devices

Abstract: Results of charge collection measurements on GaAs devices bombarded with single alpha particles are presented Experimental evidence is given which demonstrates that charge funneling and recombination play important roles in the charge collection process The data are consistent with an average distance for prompt charge collection of nearly twice the equilibrium depletion region width Comparison of the present results with existing charge funneling models is made and reasonable agreement is obtained Comparing charge collection data for GaAs and Si devices indicates that they are comparable in their susceptibility to single-event upset caused by prompt charge GaAs devices have a significant advantage in terms of total collected charge

Generalized theory of conduction in schottky barriers

Abstract: An approximate analytical expression is obtained for the non-equilibrium carrier density throughout the depletion region of a Schottky diode. This expression is used to obtain a generalized expression for the J-V characteristics of the diode. It is shown that for the case of the mean free path less than a fraction of the Debye length the current approaches the Schottky diffusion-limited result. On the other hand for the mean free path greater than this amount the current approaches Bethe's thermionic result. Furthermore, knowing the non-equilibrium carrier density permits the calculation of the transit time of the carriers through the depletion region.

Analysis of nonexponential transient capacitance in silicon diodes heavily doped with platinum

Abstract: An analysis having improved rigor has been made of the capacitance transient due to thermal emission from charged defect centers in a semiconductor depletion region. This analysis extends the range of applicability of capacitance–transient defect characterization techniques to nonexponential transient conditions which occur in diodes with trap densities of the same order as the net shallow dopant density or in diodes with somewhat smaller trap densities when defect centers are charged initially in only a part of the depletion region. An example of the improvement is shown for three silicon diodes heavily doped with platinum.

The complete doping profile using MOS CV technique

Abstract: Methods for determining the doping profile from the semiconductor surface to the deep bulk using the high frequency CV technique are presented. The analysis includes: (i) surface analysis using an improved Ziegler's method, (ii) depletion region with the surface state detection, and (iii) deep depletion region with the minority carrier generation correction. Experimental data shows precise bulk doping concentration can be obtained despite significant minority carrier generation.

MIS high-voltage element with high-resistivity gate and field-plate

Abstract: By the use of high-ohmic polycrystalline silicon(poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Numerical modeling of looped C-V Characteristics in Ap+n junction containing mid-bandgap electron traps

Abstract: The capacitance of p+n junctions containing traps or deep centers depends on the time variation of the applied reverse voltage. Capacitance changes results from the time dependent variation of the density of traps filled with electrons within the depletion region. If a cyclical reverse voltage in applied to the junction, capacitance hysteresis due to the time-dependent charge variation within the depletion region should be observed. The hysteresis loops, as a function of the bias drive rate, temperature, and total concentration of traps provide some information on the characteristics of the traps. This paper presents a numerical analysis of looped C-V characteristics in a p+n junction containing midbandgap electron traps and also discusses the variation of loops as a function of the bias drive rate, dV/dt, total concentration of traps, NT, and emission rates of electrons and holes, en and ep, based on our numerical modeling.

New modeling of GaAs MESFET's

Abstract: A first theoretical analysis is given based on a new model of GaAs MESFET's which considers the inherent effects of a free-surface depletion layer between source and gate as well as between gate and drain. Change of surface potential according to the input gate voltage causes variable series resistance and variable gate capacitance to be added to the intrinsic FET. The parasitic effects are now quantitatively estimated and an improved guideline for the design and the fabrication process is given. Detailed calculation of the effects of device parameters for recessed gate structure and some comments on the optimization of n+-layers in self-aligned structure are included. The effects of the interfacial depletion layer between active layer and substrate is also estimated in terms of drain voltage and the ratio of total deep levels density in the substrate to donor density in the active layer.

A comparison of etched-geometry and overgrown silicon permeable base transistors by two-dimensional numerical simulations

Abstract: Etched-geometry and overgrown Si permeable base transistors (PBT's) are compared by using two-dimensional numerical simulations. Because of the asymmetry of the etched structure, two biasing conditions are possible (etched-collector and etched-emitter) and both are considered. The base-to-collector transfer characteristics of PBT devices have two regions of operation. At low base-to-emitter voltages, barrier-limited current flow is observed, The two-dimensional nature of the depletion region near the Schottky-contact base grating results in a smaller electron barrier and thus a larger collector current in the etched structures than in the overgrown structure. At high base-to-emitter bias levels, charge is limited from entering the base region of the etched-emitter structure and from leaving the base region of the etched-collector device. The resulting parasitic feedback effects lead to a deviation from the square-law behavior found in the collector characteristics of the overgrown PBT. Because of the absence of semiconductor material directly above the base grating lines in the etched devices, these structures have lower device capacitances. They also have smaller transconductances at high base-to-emitter voltages. The important consequence of this is that overgrown and etched structures have comparable predicted maximum values of the small-signal unity short-circuit current-gain frequency and maximum frequency of oscillation. Fabrication-related effects are discussed qualitatively and GaAs PBT operation is considered in light of the present simulations.

Stability of generation-recombination induced dissipative structures in semiconductors

Abstract: A class of generation-recombination models involving one type of carriers and several impurity levels is studied. Far from equilibrium, impact ionization can lead to bistability of the homogeneous steady state resulting inS-shaped current-voltage characteristics, and to stationary spatial structures. It is shown for large samples that kink-shaped coexistence profiles are stable, while plane depletion or accumulation layers and cylindrical current filaments are unstable under constant voltage conditions, but can be stabilized by a constant current. The unstable mode is calculated analytically for wide and for narrow depletion layers. The critical slowing-down of this mode is established explicity as a function of the external electric field; it occurs when the threshold or holding field of the switching transitions, or the coexistence field of homogeneous phases is approached. It is shown that the hysteresis cycle of the switching transitions can be shortened by sufficiently large localized fluctuations inducing the nucleation of current layers or filaments.

Mos semiconductor device

Abstract: PURPOSE:To contrive to improve the mobility by thickening the channel at the time of ON-operation by a method wherein an n-layer in n-channel and a p-layer in p-channel are buried in the substrate distant from the interface between an oxide film and a semiconductor CONSTITUTION:The n-channel part is composed by dividing into an inside p2 layer 8 and a surface p1 layer 10 and burying a p-layer 9 therebetween In an enhancement type FET, the n-layer 9 is set generally at a lower concentration than that of the p2 layer 8 and completely depleted owing to a depletion layer extending from the p1 layer 10 and the p2 layer 8, therefore electrons contributed to conduction do not exist Next, when an inversion layer is induced in the p1 layer 10 by applying a positive potential to the gate 5, and the whole p1 layer 10 becomes an n type inversion layer by a high gate potential, then electrons generate also in the depleted n-layer 9, resulting in the ON-state of most part of the p1 layer 10 and the n-layer 9 by conversion into the n-channel Since the buried n-layer 9 is also contributed as the channel in this invention, the channel width increases effectively, and dispersion in the channel decreases, causing the improvement of the mobility

Analytical solutions for avalanche-breakdown voltages of single-diffused gaussian junctions☆

Abstract: Closed-form solutions of the potential difference between the 2 edges of the depletion layer of a single diffused Gaussian p-n junction are obtained by integrating Poisson's equation and equating the magnitudes of the positive and negative charges in the depletion layer. By using the closed form solution of the static Poisson's equation and Fulop's average ionization coefficient, the ionization integral in the depletion layer is computed, which yields the correct values of avalanche breakdown voltage, depletion layer thickness at breakdown, and the peak electric field as a function of junction depth. Newton's method is used for rapid convergence. A flowchart to perform the calculations with a programmable hand-held calculator, such as the TI-59, is shown.