Showing papers on "Depletion region published in 1988"

Heterojunction bipolar transistor

Abstract: In a first heterojunction bipolar transistor (HBT) of the present invention, base layers and collector layers are respectively divided into a plurality of layers and one of the base layers provided closer to the collector layer reiogn is set lower in impurity concentration than the other thereof provided closer to an emitter layer, thus solving a problem that thermal histories during epitaxial growth or during processes cause a set impurity distribution to be destroyed due to diffusion and thus a heterojunction is shifted from a p-n junction. Since minority carriers in the base can smoothly flow toward the collector, there can be realized an excellent HBT having a very high current gain and a very high cut-off frequency. In a second HBT of the invention, a base region comprises a first base layer of a low concentration having the same energy band gap as an emitter region and to be changed to a complete depletion layer in a thermally balanced state and a graded second base layer of a high concentration, and the first and second base layers form a heterojunction, thereby realizing an excellent HBT having a high speed performance which can exhibit a sufficient grading effect while preventing deterioration of an emitter-base voltage withstanding characteristic.

Low-field low-frequency dispersion of transconductance in GaAs MESFETs with implications for other rate-dependent anomalies

Abstract: A theory that emphasizes the role of surface states in the operation of GaAs MESFETs and that is intended to tie together hitherto unconnected anomalies in device behavior is presented. Such undesirable effects are consistent with the DC and microwave characteristics of the FET being modified by charge exchange with surface states. Generally speaking, these states are relatively slow, having characteristics frequencies of typically 1 kHz, but they nevertheless affect the microwave scattering parameters of the FET through the distortion they introduce to the shape of the depletion region in the transistor under given bias conditions. It is argued that the FET structure behaves as natural 'probe' of surface states and so constitutes a useful analytic tool for studying states on a variety of unpassivated and passivated surfaces. >

Fundamental oscillations up to 200 GHz in resonant tunneling diodes and new estimates of their maximum oscillation frequency from stationary‐state tunneling theory

Abstract: Fundamental oscillations have been measured up to 200 GHz in resonant‐tunneling diodes at room temperature. Oscillations in the range 102–112 GHz were achieved with diodes mounted in a WR‐6 waveguide resonator, and the peak output power in this range was approximately 5 μW. The same diodes oscillated between 192 and 201 GHz and generated about 0.2 μW when mounted in a WR‐3 resonator. The estimated maximum oscillation frequency ( fmax) for these devices is 244 GHz, assuming the average drift velocity across the depletion layer to be 4×107 cm s−1. This estimate has been obtained from a new phenomenological theory of the negative differential conductance which accounts for the frequency‐dependent spreading resistance and transit‐time delay. The theory is also used to show that diodes having fmax exceeding 600 GHz are feasible simply by modifying the doping profile in the regions on either side of the double‐barrier structure.

A study of the leakage mechanisms of silicided n+/p junctions

Abstract: Leakage mechanisms for shallow, silicided, n+/p junctions have been investigated. This study consists of two parts: (a) the isolation of the processing steps that cause junction leakage, and (b) the study of the mechanism for a particular process that causes leakage. Reactive ion etching, improper junction, silicide formation procedures, ion mixing, and mechanical stress are found responsible for junction leakage, although through different mechanisms. Two mechanisms have been identified for junction leakage: (a) generation centers in the depletion region caused by deep levels from damage, or from impurities, and (b) Fowler–Nordheim tunneling caused by irregularities at the silicide/silicon interface at high reverse bias. Junction leakage can be avoided by carefully designing the details of silicide and junction formation and by carefully fine‐tuning the processing steps to prevent damage of the Si substrate after forming the junction. The best junctions are made by implanting As into CoSi2 and by driving the As into Si from the silicide at 800 °C. The lower temperature drive is possible since all ion damage is contained within the silicide, leaving no damage in the Si substrate to anneal out. Very shallow, silicided, n+/p junctions can be fabricated reproducibly. These junctions demonstrate the same electrical characteristics as deeper, nonsilicided junctions, indicating that there is no fundamental barrier prohibiting fabrication of low‐leakage, silicided junctions.

Analysis of depletion edge translation lightwave modulators

Abstract: Presents a complete analysis of waveguide phase modulators based on the depletion-edge-translation concept. The phenomena taking place inside the depletion region which contribute to changing the refractive index there are studied. It is shown that the behavior of these modulators can be understood in terms of two electric field-related and two carrier-related effects: linear electrooptic, electrorefractive, plasma, and band filling. The sum of the refractive index variations produced by each one of these effects, taking into account the waveguide geometry, accounts quantitatively for the experimental phase shifts measured in the devices. No fitting parameters are used and a very good agreement between theory and experiment is obtained. Based on this theory, an analysis of the device is made in terms of the optimum values for the doping in the waveguide, and also in terms of the wavelength dependence of the device phase modulation properties. >

A new effect at high currents in heterostructure bipolar transistors

Abstract: Large current densities in heterostructure bipolar transistors with heterostructure collectors are shown to cause an excess electron barrier leading to an increase in minority-carrier charge storage in the base and a decrease in current gain of the device. This effect occurs at current densities where the mobile charge in the collector depletion region significantly reduces the electrostatic field, thus exposing an electron chemical potential barrier due to bandgap grading at the junction. The effect appears at lower current densities than the Kirk effect and should occur in wide-gap heterostructure collector devices. The effect is demonstrated using experimental data and analyzed using device modeling; solutions are suggested for its elimination. >

High-frequency performance limitations of millimeter-wave heterojunction bipolar transistors

Abstract: Heterojunction bipolar transistor structure (HBTs) with 0.25-, 0.4-, and 0.6- mu m emitter stripe widths and ultrasubmicrometer base widths, which are designed to achieve minimum transit time and low parasitic effects, are examined for their millimeter-wave performance. In particular,the dependence of the unity current gain frequency (f/sub tau /), the maximum oscillation frequency (f/sub max/), and the stability of power gains on the device structure and material parameters are critically analyzed. It is shown that the classical f/sub max/ expression commonly used for bipolar transistors, involving the effective carrier transit time and the collector-based RC time constant does not adequately represent the performance of ultrasubmicrometer-based-width HBTs, where the transadmittance phase delay associated with the collector-base depletion layer transit time and the parasitic collector-based capacitance are significant. The expected ballistic and quasiballistic behaviour of electron in these ultrasubmicrometer structures, if properly designed, minimizes the effective carrier transit time effect, but its impact on the f/sub max/ by the excess transadmittance phase delay poses a more fundamental and serious high-frequency limiting factor for the realization of millimeter-wave HBTs than has been hitherto recognized. The accuracy and usefulness of the proposed analytical approach is demonstrated for a practical HBT structure with 1.2- mu m emitter stripe design, giving results that agree well with measurements. >

Model for hysteresis and kink behavior of MOS transistors operating at 4.2 K

Abstract: The hysteresis and kink characteristics of MOS transistors (MOSTs) operating at 4.2 K have been investigated. The response time of a MOST depends exponentially on the inverse of the drain voltage. A model is proposed that explains both the transient and kink behavior of the devices. It is based on the forced formation of the depletion layer caused by the avalanche-generated substrate current. The model is compared with previous models published in the literature. >

Insulated gate field effect transistor with buried layer

Abstract: An insulated gate field effect transistor fabricated in one conductivity type semiconductor substrate wherein a source region and a drain region are formed apart each other to define a channel region therebetween, having a deep ion implantation region which is so formed in the lower portion of the channel region that at least one end portion of the depletion region of the channel extends towards the source region beyond the border between the source region and the channel region at the surface of the substrate whereby an imaginary straight line drawn from said border at the surface of the substrate and an intersecting point between the depletion region of the source and the depletion region of the channel region without a back gate bias voltage defines an angle larger than 90° against the surface of the substrate.

The MOS depletion-mode thyristor: a new MOS-controlled bipolar power device

Abstract: A new MOS-bipolar power device in which forced-gate turn-off is achieved using a depletion region formed by an MOS gate structure is described. This device, called the depletion-mode thyristor (DMT), offers many highly desired features for high-voltage power switching applications: a) low ON-state drop, b) high input impedance, c) three-terminal operation, d) equivalent complementary devices, and e) high maximum controllable current. Experimental verification of device operation has been achieved using a UMOS gate technology. >

Drain avalanche breakdown in gallium arsenide MESFET's

Abstract: Avalanche breakdown in GaAs MESFET's simulated by two-dimensional (2-D) numerical calculation with a two-carrier model. The simulation involves electron-hole pair generation due to impact ionization and employs a simplified model of the surface depletion layer of GaAs. Gate-bias-dependent drain breakdown voltage is demonstrated. The effect of the surface depletion layer, drain-to-gate spacing and n/sup +/ layer under the drain contact upon the breakdown voltage is demonstrated. It is clarified that the surface depletion layer has a pronounced effect on the gate-bias dependence of the breakdown voltage. The breakdown mechanism is explained in terms of conductivity modulation in the semi-insulting substrate. >

Numerical study of emitter-base junction design for AlGaAs/GaAs heterojunction bipolar transistors

Abstract: The DC common-emitter current gains of abrupt- and graded-junction heterojunction bipolar transistors (HBTs) are studied and compared by numerical simulation. Electron injection across abrupt emitter-base heterojunctions is evaluated by numerically solving the wave equation. A numerical model based on drift-diffusion carrier transport is used for graded-junction HBTs and to assess recombination currents in both the structures. The results demonstrate that the increase in injected electron current afforded by compositional grading is accompanied by an increase in recombination within the space-charge layer. As a result, neither design option has a clear advantage with respect to common-emitter current gain. >

Two-dimensional simulation of submicrometer GaAs MESFETs: surface effects and optimization of recessed gate structures

Abstract: The surface potential effect in GaAs MESFETs causes a depleted zone to form not only between the source and gate, but also between the gate and drain. The consequences of this phenomenon on the device behavior, the DC and AC characteristics, and the expected performance are studied. For this purpose, a two-dimensional resolution of the basic semiconductor equations is used. This model takes into account relaxation effects by including an energy relaxation equation. The dependence of MESFET characteristics such as transconductance, output conductance, and capacitance on the dimensions of the zone where surface potential effects occur is given. Some interesting conclusions concerning the optimization of recessed-gate structures are drawn. >

Noninvasive method and apparatus for characterization of semiconductors

Abstract: A method and apparatus are described for characterizing a semiconductor using the surface photovoltage (SPV) effect. A region of the surface of the semiconductor is illuminated with an intensity modulated beam of light, the wavelength of the light being shorter than that corresponding to the energy gap of the semiconductor. The surface photovoltage (SPV) induced in the semiconductor is measured under bias voltage conditions. The intensity of the light beam and the frequency of modulation are selected such that the surface photovoltage (SPV) is directly proportional to the intensity and reciprocally proportional to the frequency of modulation. Using the surface photovoltage (SPV) and the bias voltage (V g ) measurements, the charge induced in the semiconductor space charge region (Q sc ) and the charge induced in the semiconductor (Q ind ) are determined. This information is used to determine various parameters of the semiconductor including surface state density and oxide/insulator charge. The technique is designed especially for use in characterizing semiconductor wafers, coated or uncoated, but may, if desired, also be used in characterizing MIS or MOS type semiconductor devices.

CMOS having buried layer for carrier recombination

Abstract: In order to improve latchup withstanding capability, a CMOS device is provided with at least one recombination layer which is buried in either or both substrate regions of a pMOS and a nMOS at such a position that a depletion layer formed at a pn junction between both substrate regions of the pMOS and nMOS does not reach the recombination layer. The recombination layer is a polycrystalline silicon or amorphous silicon layer having plentiful carrier recombination centers, or a layer having plentiful traps formed by ion implantation, or a layer of a compound semiconductor having a small band gap.

Scanning tunneling spectroscopy of oxygen adsorbates on the GaAs(110) surface

Abstract: Spatially resolved measurements of the tunneling current versus applied voltage are obtained for oxygen adsorbed on the GaAs(110) surface, using a scanning tunneling microscopy (STM) Effects with different length scales are observed, arising from two sources of charge in the system: negatively charged adsorbates and a positively charged space charge layer The space charge layer produces band bending on n‐type material, which is observed as a shift in the onsets for tunneling out of and into the valence and conduction bands, respectively We analyze these shifts using theoretical calculations of the tunneling current through surface space charge layers Directly above an oxygen adsorbate on n‐type material, an enhancement in tunneling is observed near the top of the valence band edge, while a corresponding decrease is observed near the bottom of the conduction band This local behavior is identified as arising from changes is the surface density‐of‐states produced by the Coulomb potential of the charged

Self-aligned Bi-CMOS device having high operation speed and high integration density

Abstract: A Bi-CMOS device comprises a first insulating layer formed on a principal surface of a semiconductor substrate to extend outwardly from an edge portion of a base region of a bipolar transistor and from an edge portion of each source/drain region of each MOS transistor. A first polycrystalline semiconductor layer is formed on and in contact with a surface area of the base region of the bipolar transistor and a surface area of each source/drain region of each MOS transistor so as to extend on the first insulating layer. A second insulating layer is formed to cover the first polycrystalline semiconductor layer, a base-emitter junction exposed at the principal surface of the substrate and a portion of each of the base region and the emitter region adjacent to the exposed base-emitter junction. The second insulating layer also covers an inside edge of each source/drain region of the MOS transistors, and portions of each source/drain region and a channel region adjacent to the inside edge. A second polycrystalline semiconductor layer is formed to cover a gate insulator of each MOS transistors and a portion of an emitter region of the bipolar transistor in contact with the emitter region, so as to extend on the second insulating layer.

Fabrication of one-dimensional GaAs wires by focused ion beam implantation

Abstract: Novel, simple techniques were developed to fabricate very narrow GaAs conducting wires by utilizing direct focused ion beam (FIB) implantation. We employed two methods for fabrication of the wires. The first method makes use of high‐resistivity (HR) regions formed by FIB implantation without successive annealing to define a very narrow conducting wire (HR method). In the second one, focused Si ions are line implanted into p‐type GaAs, forming an n‐type conducting wire in the p‐type region. Then, reverse‐bias is applied across the pn junction in order to make the wire narrower by expanding the depletion layer (PN method). This structure has an advantage that the thickness of the wire can be varied by bias voltage. Magnetoconductances measured in all the fabricated wires show evidences of weak electron localization and conductance fluctuations due to a quantum interference effect. The minimum widths of the wires are evaluated to be ∼20 nm (HR method) and ∼100 nm (PN method) by fitting the theory of one‐dime...

Semiconductor radiation detector

Abstract: A structure of semiconductor radiation detector element having a p-n junction comprises a substrate layer including a radiation absorbing layer having a silicon equivalent thickness not smaller than 140 μm and located adjacent to a depletion layer formed at the p-n junction With the simplified structure, both the detection sensitivity and the energy compensating performance are enhanced significantly

Monte Carlo study of the influence of collector region velocity overshoot on the high-frequency performance of AlGaAs/GaAs heterojunction bipolar transistors

Abstract: Detailed Monte Carlo calculations of electron transport in the base-collector junctions of heterojunction bipolar transistors are reported. In particular, the author focused on velocity overshoot in the collector region and its influence on collector transit time. Very high peak electron velocities (7-9*10/sup 7/ cm/s) were observed over narrow regions just inside the collector (300-500 AA). However, the effects of velocity overshoot on reducing the total collector transit time were found to be marginal and the transit times were not very different from what would be predicted by assuming a constant saturated drift velocity of 10/sup 7/ cm/s throughout the collector depletion layer. The calculations presented here confirm that Y. Yamauchi and T. Ishibashi (1986) greatly overestimate the contribution to transistor performance from velocity overshoot in the collector region. >

Optical semiconductor device and method of manufacturing the same

Abstract: A P-type epitaxial silicon layer is formed between an N-type epitaxial layer and a P + -type semiconductor substrate An impurity concentration profile is formed in at least one region of the P-type epitaxial silicon layer to decrease with an increase in distance from the substrate and toward the N-type epitaxial layer A depletion layer is formed as a function region (P-N junction) between the P-type epitaxial silicon layer and the N-type epitaxial layer Carriers are generated when light is incident on the depletion layer Carriers are also generated in a region of the P-type layer deeper than the depletion layer A self-electric field is formed in the P-type epitaxial silicon layer by the impurity concentration profile, which is lowest at the junction The carriers generated in this manner are accelerated by the self-electric field and flow rapidly into the function region As a result, an optical semiconductor device according to the present invention has good response characteristics

Neutron irradiation effects on AlGaAs/GaAs heterojunction bipolar transistors

Abstract: AlGaAs/GaAs heterojunction bipolar transistors irradiated with 10/sup 15/ neutrons/cm/sup 2/ demonstrated superior performance to silicon bipolar transistors. The postneutron current gain was dominated by recombination in the emitter-base depletion region. The base current exhibited an ideality factor n>2 after irradiation, which was attributed to two possible recombination mechanisms associated with neutron-induced traps: tunneling-assisted trapping and recombination arising from a nonuniform distribution of Shockley-Read-Hall centers within the depletion region. The emitter-base heterojunction was degraded more than the collector-base homojunction after irradiation. >

Microstructure fabrication and transport through quantum dots

Abstract: We report the microfabrication techniques used to produce devices which study electronic transport through quantum dots Molecular‐beam epitaxy, electron‐beam lithography, and reactive ion etching have been utilized in this effort The minimum physical lateral size of the dots reported here is 01×02 μm Transport shows some degradation in I–V characteristics with respect to much larger resonant tunneling diodes Current densities observed suggest the electrical size of diodes is smaller than the physical size A surface depletion region of 500 A may account for this effect Telegraph noise is observed as a result of single electron trapping in the structure No clear evidence of lateral quantization has been observed

Depletion charge measurements by tunneling spectroscopy GaAs-GaAlAs field-effect transistors

Abstract: The subband energies on GaAs‐GaAlAs field‐effect transistor samples were measured by tunneling spectroscopy using a structure, where the tunneling process starts from an accumulation layer, and a conventional structure, where the electrons tunnel from a metal electrode into the two‐dimensional electron gas. Self‐consistent calculations were performed to determine the depletion charge from the measured subband energies. Furthermore, the influence of a backgate voltage was investigated both experimentally and theoretically. As far as we know, this is the first direct determination of the depletion charge in GaAs‐GaAlAs field‐effect transistor structures.

Minority-carrier lifetime analysis of silicon epitaxy and bulk crystals with nonuniformly distributed defects

Abstract: Existing analyses of the pulsed response of an MOS capacitor for minority-carrier lifetime determination result in a lifetime value averaged over most of the depletion region width. The authors present an analysis of MOS capacitance-versus-time data that enables minority-carrier generation lifetime to be plotted as function of depletion-region depth. The technique is shown to be useful for samples with bulk or buried interfacial layer defects that have defect-free surfaces. Data are presented for intrinsically gettered bulk crystals and extrinsically gettered Si (2%Ge) epitaxial layers with misfit dislocations. For samples that do have uniform lifetimes, the measurement time required for determining carrier lifetime is reduced by more than an order of magnitude. >

Evaluation method for semiconductor device

Abstract: An evaluation method for a semiconductor device includes the steps of applying a reverse bias voltage between an N-type substrate formed in a surface of the semiconductor device and a P-type region formed in a surface of the N-type substrate to form a depletion layer along the junction therebetween, scanning the surface of the semiconductor device is one direction with a light beam to cause an optical beam induced current to be flow across the junction, and measuring the OBIC intensity profile on a scanning line extending across the depletion layer in the surfaces of the N-type substrate and P-type region. In the method, the light beam has a wavelength whose penetration length is smaller than the depth or thickness of the P-type region, the OBIC intensity profile is integrated over a range corresponding to the depletion layer, and the integrated value is normalized by the reverse bias voltage to determine the surface potential distribution of the semiconductor device.

Semiconductor-based radiation-detector element

Abstract: A semiconductor-based radiation-detector element particularly adapted to neutron detection, and the method for making the same, in which a high sensitivity single-crystal semiconductor substrate has diffused therein at-least-one region of 3 He gas, which remain resident therein, whereby, upon application of an inverse bias to the junction in the semiconductor substrate, the colliding of incident neutrons with the resident 3 He gas results in a reaction which produces hole-electron pairs in the depletion layer within the semiconductor, those hole-electron pairs producing output electrical pulses which appear at the output terminals of the detector for utilization by detection and measuring apparatus connected to the semiconductor-based radiation-detector element.

Radiation hardened semiconductor device and method of making the same

Abstract: An N-channel transistor (30) formed in a layer of semiconductor material (34) disposed on an insulating substrate (32) is disclosed. The source region (48) has a depth less than the thickness of the semiconductor layer (34) so that a P-type region (44) can be formed in the semiconductor layer (34) between the source region (48) and the insulating substrate (32). This P-type region (44) has an impurity concentration sufficient to prevent the depletion region of the source (48) from extending to the interface between the layer of semiconductor material (34) and the substrate (32). The P-type region (44) substantially prevents back-channel leakage currents from flowing between the source region (48) and the drain region (50) along the portion of the layer of semiconductor material (34) immediately adjacent the insulating substrate (32) when the device has been irradiated.