Showing papers on "Depletion region published in 1989"

Oscillations up to 420 GHz in GaAs/AlAs resonant tunneling diodes

Abstract: We report room‐temperature oscillations up to frequencies of 420 GHz in a GaAs resonant tunneling diode containing two 1.1‐nm‐thick AlAs barriers. These results are consistent with a recently proposed equivalent circuit model for these diodes in which an inductance accounts for the temporal delay associated with the quasibound‐state lifetime. They are also in accordance with a generalized impedance model, described here, that includes the effect of the transit time delay across the depletion layer. Although the peak‐to‐valley ratio of the 420 GHz diode is only 1.5:1 at room temperature, we show that its speed is limited by the parasitic series resistance rather than by the low negative conductance. A threefold reduction in this resistance, along with a comparable increase in the peak‐to‐valley ratio, should allow oscillations up to about 1 THz.

Franz–Keldysh oscillations originating from a well‐controlled electric field in the GaAs depletion region

Abstract: The Franz–Keldysh oscillations induced by the electric field in the depleted zone below the GaAs surface are studied by photoreflectance spectroscopy. The electric field is precisely controlled by a molecular beam epitaxy grown buried highly doped layer and the pinned position of the Fermi level at the surface. It is shown that the electric field value as derived from theory is in disagreement with the value derived from electrostatic calculations. Consequently a determination of the Fermi level pinning is only possible from a measurement of both n‐ and p‐doped samples.

MIS transistor structure for increasing conductance between source and drain regions

Abstract: A metal-insulator-semiconductor transistor comprises an insulator layer, a semiconductor body provided on the insulator layer and comprising a source region, a drain region and a channel region extending in a first direction between and interconnecting the source region and the drain region, a gate insulator film provided on the semiconductor body so as to cover the channel region except for the part of the channel region in contact with the insulator layer, and a gate electrode of a conductive material provided in contact with the gate insulator film so as to cover the channel region underneath the gate insulator film except for the part of the channel region in contact with the insulator layer. The channel region has a width substantially smaller than twice the maximum extension of the depletion region formed in the channel region.

Implanted silicon JFET on completely depleted high-resistivity devices

Abstract: To satisfy the increasing interest in the integration of electronics onto optical and ionizing particle fully depleted detectors, a nonconventional JFET (junction field-effect transistor), designed to operate on a completely depleted, 2-k Omega -cm resistivity silicon substrate, has been designed, fabricated, and tested at room temperature. The devices show very low gate leakage current, low output conductance, a transconductance per unit gate width of 3 mS/mm, and a pinch-off voltage of -1.5 V. The integration of the devices onto the detectors makes possible the matching of the input capacitance of the JFET to the detector's output capacitance, which is of the order of few hundreds of femtorads. The measured gate capacitance of 200 fF is shown to correspond to an expected resolution in charge measurements, at room temperature, of less than 40 electrons rms. The fabrication constraints, imposed by the limited number of production steps of the detectors, are reported. >

Degradations due to hole trapping in flash memory cells

Abstract: Degradation in the hot-electron programmability of the flash memory cell is observed after erasing from the drain. Trapped holes in the oxide near the drain junction are found to be responsible for this degradation. Hole trapping in the oxide also causes another problem known as gate disturb, which is the undesired increase in the threshold voltage of an erased cell during programming of the other cells on the same word line. Threshold-voltage shifts due to gate disturb are used to monitor the amount of trapped holes in the oxide after cell erasure. It is determined that the trapped holes are mainly externally injected from the junction depletion region rather than directly generated in the oxide by the Fowler-Nordheim (F-N) tunneling process. >

Fermi threshold field effect transistor

Abstract: A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate doping, the vertical electric field in the channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Source and drain subdiffusion regions may be provided to simultaneously maximize the punch-through and impact ionization voltages of the devices, so that short channel devices do not require scaled-down power supply voltages. Multi gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance. The Fermi-FET criteria may be maintained, while allowing for a deep channel by providing a substrate contact for the Fermi-FET and applying a substrate bias to this contact. Substrate enhancement pocket regions adjacent the source and drain regions may be provided to produce a continuous depletion region under the source, drain and channel regions to thereby minimize punch-through effects.

Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology

Abstract: The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900 degrees C/30 min to rapid thermal annealing at 1050 degrees C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G/sub m/ of NMOS transistors with 125-AA Gate oxide thickness.

Resonant tunneling diodes for switching applications

Abstract: Rise times for simple pulse‐forming circuits are presented. Switching times for present best devices are in the range of 5–15 ps. An equivalent circuit model for resonant tunneling diodes inclusive of space‐charge effects and transit time effects in the depletion region is presented. From these models it is shown that switching times are limited by the device RC time constants and are relatively unaffected by the resonant state lifetime or depletion layer transit times. Appropriate figures of merit for switching applications are the device capacitance and peak current density. Less emphasis should be placed on improving the peak‐to‐valley ratio. Optimally designed devices which maximize the current density should be capable of switching in under 5 ps.

Spatially resolved and energy-resolved defect kinetics in a-Si:H: A comprehensive study by phase-shift analysis of modulated photocurrents.

Abstract: The analysis of modulated photocurrents is reviewed, and a novel experimental technique for measurements of modulated photocurrents over a wide frequency range is applied to undoped a-Si:H in sandwich contact configuration. By analysis of the phase response the energetic as well as spatial (versus distance to the top contact) distribution of gap states above midgap is obtained. Metastable changes in the gap-state distribution by light soaking (Staebler-Wronski effect) and by depletion bias annealing are studied as a function of illumination time, illumination temperature, annealing time, annealing temperature, and applied bias during annealing. The main experimental results are as follows: Undoped a-Si:H exhibits a peak in the distribution of gap states at about 0.6 eV below the conduction-band edge ${E}_{c}$ and in the depletion region a peak of shallow states at 0.4 eV below ${E}_{c}$. Upon light soaking the deep peak increases according to a power law and the shallow one is quenched. The original distribution is restored by annealing above 420 K. At lower degradation temperatures, creation and quenching rates are enhanced but the established changes are less stable against annealing. Both peaks show exponential tails towards midgap with slopes that depend on annealing and degradation temperatures. Activation energies for annealing of deep states show a broad variation between 0.9 and 1.3 eV and are strongly correlated with the energetic position of the defect states in the gap. Annealing with depletion bias produces a metastable increase of both defect peaks above midgap. Based on the thermodynamical considerations and on theoretical calculations of the dangling-bond correlation energies, a model of the defect structure is discussed that is able to account for the presented results as well as various other experimental observations concerning metastable changes and the energetic position of defects in amorphous silicon.

Effects of oxygen impurities in W films on W/GaAs Schottky‐barrier contacts

Abstract: Schottky‐barrier characteristics and chemical reactions of contacts between oxygen‐contained W films and GaAs substrates annealed up to 800 °C have been investigated. Phase transformation from β‐W to α‐W of the oxygen‐contained W films (3 at. % oxygen), sputter deposited in Ar and O2 gas mixture, is observed at temperatures around 650 °C. Electrical degradation of the contacts, especially in capacitance‐voltage (C‐V) characteristics, is found after annealing above 650 °C. Oxygen accumulation at the W/GaAs interfacial region and Ga and As atom diffusion into the W films are found by secondary‐ion mass spectrometry during annealing. Formation of a Ga2O3 layer at the interfacial region is also detected by x‐ray photoemission spectroscopy and transmission electron microscopy. These results suggest that Ga2O3‐layer formation is related to the electrical degradation. The C‐V characteristics can possibly be explained by series capacitance of an interfacial oxide layer and a depletion layer together with an assum...

Semiconductor device having intermediate layer for pinching off conductive path during reverse bias application

Abstract: A semiconductor device comprising a semiconductor substrate (30) having two major surfaces, cathode elec­torde film (32) formed on the first major surface of the substrate (30), and anode electrode film (34) made of a Schottky-barrier metal such as titanium (Ti, Mo, V), formed on the second major surface of the substrate (30). The substrate (30) is formed of an N⁺-type layer (36) formed on the cathode electrode film (32), an N⁻-type layer (38) formed on the N⁺-type layer (36), an N⁻⁻-type layer (40) formed on the N⁻-type layer (38) and having an impurity concentration lower than that of the N⁻-type layer (38), and an N⁻-type layer (42) interposed between the N⁻⁻-type layer (40) and the anode electrode film (34). The device further comprises a plurality of P⁺-type areas (46) formed in the second major surface of the substrate (30), contacting the anode electrode film (34) and extending through the N⁻-type layer (42) and the N⁻⁻-type layer (40) into the N⁻-type layer (38). When a forward bias is applied to the device, a current flows from the anode electrode film (34), passes through the N⁻-, N⁻⁻-, N⁻- and the N⁺-type layers (42, 40, 38, 36), and flows out of the cathode electrode film (32). When a reverse bias is applied to the device, the depletion layer formed around the junction between each P⁺-type area (46) and the N⁻⁻-type layer (40) extends, joining with the similar depletion layers, thereby pinching off the path of the current. As a result, the flow of a reverse leakage current is suppressed.

Coupled plasmon and phonon excitations in the space-charge layer on GaAs(110) surfaces

Abstract: High-resolution electron-energy-loss spectroscopy (HREELS) is used to study the surface plasmon and phonon in the space-charge layer on doped GaAs(110) cleaved surfaces. Three losses are observed, with energies of about 27, 36, and 42 meV. The peak at 36 meV is attributed to an unscreened phonon in the depletion layer. The other two losses are due to the coupled modes of the plasmon and phonon propagating near the interface of the depletion layer and the bulk. The surface Fermi-level pinning is induced either by residual-gas interaction with the surface or by deliberate hydrogen adsorption; this in turn modifies the depletion-layer thickness. This modification results in a quite pronounced change of the relative intensities and noticeable energy shifts of these losses. A model energy-loss spectrum calculated in the framework of local-response theory is used to deduce the properties of the space-charge layer. Our model is the first to use a self-consistent free-carrier profile together with the Lindhard description of the local dielectric response.

Planar semiconductor device having high breakdown voltage

Abstract: A planar semiconductor device having a high breakdown voltage includes a semiconductor layer of a first conductivity type and a first semiconductor region of a second conductivity type selectively formed, together with the semiconductor layer, in the surface of the semiconductor layer forming a pn junction. The first semiconductor region is formed to have an impurity concentration higher than that of the semiconductor layer and therefore a resistivity higher than that of the semiconductor layer. A second semiconductor region of the second conductivity type having an impurity concentration lower than that of the first semiconductor region, is formed around and in contact with the first semiconductor region and together with the semiconductor layer constitutes a pn junction. A high resistance film is formed at least over the first semiconductor region and the second semiconductor region. A voltage is applied across the high resistance film to create a uniform electric field in the high resistance film.

Semiconductor device and photoelectric conversion apparatus using the same

Abstract: A semiconductor device comprises at least an emitter region of a first conductivity type, a base region of a second conductivity type, and a collector region of a first conductivity type. The base region essentially consists of Si1-XGeX (0 < X < 1), further comprises regions formed in a depletion layer close to an interface between the base region and the collector region or in the collector region and in a depletion layer close to an interface between the base region and the emitter region or in the emitter region, and has a larger Ge amount at the base region side and a smaller Ge amount at the emitter and collector sides.

Microwave noise performance of InP/InGaAs heterostructure bipolar transistors

Abstract: The authors report the first low-noise InP/InGaAs heterostructure bipolar transistor (HBT). Minimum noise figures of 0.46, 2.0, and 3.33 dB were measured at 2, 10, and 18 GHz, respectively. The noise performance of this InP/InGaAs HBT with an emitter size of 3.5*3.5 mu m/sup 2/ is compared to that for FETs having a 1- mu m gate length. The measured minimum noise figures agree well with calculated data using a modified Hawkins model. Broadband low-noise operation is observed because of the short transit time for injected nonequilibrium electrons to transverse the base and collector depletion region. >

Reduction of electric field effect in the bird's beak region of a DRAM cell following expansion of active region through local encroachment reduction

Abstract: The present invention constitutes an improvement of the Local Encroachment Reduction (LER) process developed by Tyler Lowrey at Micron Technology, Inc. of Boise, Idaho. LER consists of selectively etching a portion of the field oxide which has encroached into a DRAM cell's active area and then subjecting the cell to a high-energy boron implant to maintain adequate active area isolation. Although the boron implant effectively decreases the width of the depletion region between n+ active areas and p+ substrate, it has the undesirable effect of reducing the breakdown voltage at the n-p junctions in the bird's beak regions at the edges of the active regions, thus increasing the cell's susceptibility to gated-diode breakdown following creation of the cell plate. The present invention solves this problem by creating a graded junction in the bird's beak regions of the cell. The graded junction reduces the electric field intensity in the junction region, resulting in an increase in the breakdown voltage. The graded junction also minimizes the effect of gated-diode breakdown and band-band tunneling leakage.

Numerical simulation of AlGaAs/GaAs heterojunction bipolar transistors with various collector parameters

Abstract: Numerical simulations of AlGaAs/GaAs HBTs (heterojunction bipolar transistors) with various collector parameters are carried out to investigate the cutoff frequency characteristics, using the conventional static model and the energy transport model. It is shown that the transit time in the collector depletion layer is an intrinsically more important factor than the collector charging time. Therefore, a thinner n/sup -/-layer with higher doping density is desirable to achieve higher cutoff frequency, f/sub T/. It is found that the importance of energy transport effects arises from the fact that the actual electron energy deviates strongly from the field determined energy. The velocity overshoot can occur in a graded bandgap base and in the collector depletion layer, resulting in much higher f/sub T/ than that predicted by the conventional model. A value of F/sub T/ higher than 140 GHz is expected for an HBT with an n/sup -/-layer thickness of 1000 AA. >

Field-effect transistor

Abstract: PURPOSE:To facilitate the display of a maximum current driving capability by making the thickness of a semiconductor layer of a specific value. CONSTITUTION:Gate insulating layer 2 and 3 are formed on both the main surfaces of a semiconductor layer 1 so as to face each other and gate electrodes 4 and 5 are formed outside the layers 2 and 3. A source region 6 and a drain region 7 are formed on the regions where the layers 2 and 3 are not formed. The region 6 side is grounded and a voltage applying wiring 8 is formed on the region 7 side. If the thickness of the semiconductor layer 1 is selected within a range of 500-3000Angstrom , the number of carriers is increased, the capacitance of a depletion layer is reduced and a drain current is increased.

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To shorten a distance between a source and a drain and to realize an ultrahigh-speed operation by a method wherein a semiconductor region of a different conductivity type is epitaxially grown on a substrate crystal by using an organometallic vapor growth method or a molecular-beam epitaxial method and a structure between a source and a drain is formed. CONSTITUTION:In a vertical-type MIS electrostatic induction FET (SIT) of a depletion-layer type, the spread of a depletion layer 7 is controlled by a voltage which is applied to gate electrodes 3. For its manufacturing method, an organometallic vapor growth method or a molecular beam epitaxial method is used as a crystal growth method. An optical-pumping gas etching method or a wet etching method is used as the formation method of a gate side face. Thereby, the film thickness of a p-layer and an n layer can accurately be controlled in the unit of a monomolecular layer, the p-layer can be made thin and a channel length can be set to the mean free path or lower of electrons. As a result, the electrons injected from a source electrode travels without being scattered by a crystal lattice, and a high-speed operation can be executed.

The effect of base-emitter spacers and strain dependent densities of states in Si/Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors

Abstract: The authors describe two effects which can significantly affect the transport of electrons across the base region of Si-Si/sub 1-x/Ge/sub x/-Si heterojunction bipolar transistors and limit the effective bandgap reduction. These effects are the formation of a parasitic electron barrier due to a nonabrupt base-emitter junction and the reduction of the density of states in the Si/sub 1-x/Ge/sub x/ base layer because of the anisotropic strain. Junction spacers have been found to eliminate the parasitic barriers for optimum devices. For optimum device performance it is necessary to keep the Si-Si/sub 1-x/Ge/sub x/ interfaces in the junction depletion region. The strain dependence of the densities of states in the base region lowers collector current. >

Rugged lateral DMOS transistor structure

Abstract: A lateral DMOS transistor includes a high conductivity substrate having an epitaxial layer grown thereon to have a resistivity suitable for the transistor body. A highly doped topside body contact is diffused into the epitaxial layer along with an abutting heavily doped source. The source is self-aligned with a conductive polysilicon gate lying on top of a thin gate oxide. After source diffusion the gate is oxide coated so as to be fully insulated. A main drain electrode portion is diffused near the opposing side of the gate spaced a distance away. A lightly doped drain region portion extends between the main drain region and the edge of the gate providing the required surface breakdown behavior. The main drain diffusion portion is extended into the epitaxial layer so that the spacing between the heavily doped substrate and the drain diffusion produces depletion region reach through at a voltage that is lower than the drain avalanche voltage. Several embodiments are set forth for practicing the invention.

Semiconductor device with current detecting function

Abstract: A semiconductor device with a current detecting function in which in place of an external resistor for detecting an operation current such as drain current or collector current of a device such as an FET or bipolar transistor, a probe electrode is formed in proximity to the device depletion layer to connect therethrough with the device channel to generate a probe voltage corresponding to the operation current.

Method of making an MOS transistor having improved transconductance and short channel characteristics

Abstract: A transistor is described having reduced series resistance and a reduced peak lateral electric field. The peak lateral field is reduced by forming an image charge in the surface of the substrate underlying the edges of the transistor gate electrode. The image charge is created by impregnating portions of an oxide layer overlying the source and drain regions with an impurity having the same conductivity as that of the underlying substrate. The depletion region formed in the substrate by the image charge provides a graduated electric filed in the channel preventing hot carrier injection into the gate oxide and increasing the breakdown voltage. The image charge is of an opposite conductivity to that of the substrate and is thus composed of minority carriers. The high concentration of majority carriers near the surface of the substrate lower the series resistance of the transistor thereby increasing the drive current.

Alpha-particle-induced charge collection measurements for megabit DRAM cells

Abstract: An alpha-particle-induced charge collection mechanism for megabit DRAM cells was studied using an experimental method for 1-bit cell test structures with storage areas of 1 to 30 mu m/sup 2/. The dependence of the critical charge Q/sub c/ for soft errors on the cell size and p/sup +/ barriers was extensively examined. Q/sub c/ was found to be proportional to the diagonal length of the depletion region. In addition, charge collection in the presence of p/sup +/ barriers was enhanced by charge multiplication through the weak avalanche effect. >

Calculation of the electron-beam-induced current (EBIC) at a Schottky contact and comparison with Au/n-Ge diodes

Abstract: The electron-beam-induced current (EBIC) collection efficiency n of a Schottky contact perpendicular to the electron beam of a scanning electron microscope is calculated. The continuity equation is solved for a non-uniform generation function assuming a linear variation of the electric field within the depletion zone. The recombination of the carriers at the metal-semiconductor interface is considered. Majority carrier injection from the semiconductor into the metal is found to be non-negligible for low doping level and low beam energy. It is demonstrated that the assumption of 100% collection efficiency for the minority carriers generated within the depletion zone, and the related boundary condition, lead to an overestimation of the collected EBIC intensity, particularly for short minority diffusion lengths. The present model allows a more satisfactory analysis of the experimental data obtained on Au/n-Ge Schottky contacts.

Polymer Concentration Profile near a Liquid-Solid Interface: Evanescent Wave Ellipsometry Study

Abstract: The phase retardation angle, ~~. as a function of the incident angle was measured to study adsorption and depletion of polymers near a solid substrate from a solution by use of an evanescent wave ellipsometry technique. A lightly sulfonated ionomer dissolved in a polar solvent displayed an appreciable interfacial adsorption layer, while the nonionic precursor in ethyl acetate exhibits a depleted concentration profile. The results are in good agreement with adsorption or depletion layer profiles obtained previously by other techniques, i.e., X-ray fluorescence for polymer adsorption and optical fluorescence evanesent wave technique for depletion.

Vertical field-effect transistor having a high breakdown voltage and a small on-resistance

Abstract: A vertical MOSFET includes a base region formed on the surface of a drain region, a source region provided in the base region, a first semiconductor region provided on the surface of the drain region between portions of the base region, the first semiconductor region having the same conductivity type as the drain region and an impurity concentration higher than that of the drain region, a second semiconductor region of the opposite conductivity type provided in the first semiconductor region, a gate electrode provided on the base region surrounded by the source region and the first semiconductor region, and an insulating film provided on the second semiconductor region

Nonlocal theory of collective excitations in doped semiconducting films: The effect of depletion and accumulation layers.

Abstract: We discuss the collective electronic excitations of semiconducting films, through use of the random-phase approximation, and wave functions generated from an appropriate self-consistent potential. The calculations are carried out for {ital n}-type GaAs, with depletion or accumulation layers induced by suitable charge sheets on the film surfaces. We find and discuss the properties of surface plasmons and standing-wave bulk plasmons, and in the case of a strong accumulation layer we also find collective modes localized in the accumulation region that are only weakly Landau damped even at rather large wave vectors. We apply our calculations to the description of electron-energy-loss studies of semiconducting films.