Showing papers on "Depletion region published in 1999"

Tunneling-enhanced recombination in Cu(In, Ga)Se2 heterojunction solar cells

Abstract: This letter presents an analytical model for tunneling-enhanced recombination current in the space charge region of semiconductor junctions. We investigate current–voltage characteristics of different types of Cu(In, Ga)Se2-based heterojunction solar cells in a temperature range from 100 to 340 K. The temperature dependence of the saturation current and of the diode ideality factor of these devices are well described by the closed form expressions derived by the present approach.

Depletion layer thickness and Schottky type carrier injection at the interface between Pt electrodes and (Ba, Sr)TiO3 thin films

Abstract: The electrical conduction properties of rf sputter-deposited (Ba, Sr)TiO3 (BST) films on Pt and IrO2 electrodes and metalorganic chemical vapor deposited (MOCVD) BST films on a Pt electrode were investigated and a new energy band model that satisfactorily explains the observed leakage current characteristics and film thickness dependent dielectric properties is proposed. The BST and Pt junction constituted a blocking contact with interface potential barrier heights of 1.6–1.7 eV and 1.2 eV for the sputtered and MOCVD films, respectively. Schottky emission behavior was observed at measurement temperatures higher than 120 °C and tunneling related conduction behavior appeared below that temperature for a film thickness of 40 nm. A partial depletion model with a very thin (about 1 nm) layer devoid of space charge at the interface with the Pt electrode is proposed to explain the V1/2 dependent variation of ln(Jo) as well as the decreasing dielectric constant with decreasing film thickness.

A Study of Depletion Layer Effects on Equivalent Circuit Parameters Using an Electrochemical Quartz Crystal Impedance System

Abstract: An electrochemical quartz crystal impedance system (EQCIS) was used to investigate depletion layer effects on equivalent circuit parameters of piezoelectric quartz crystal resonance in electrochemi

Modelling the electric potential distribution in the dark in nanoporous semiconductor electrodes

Abstract: This study concerns the electric potential distribution in the dark in nanocrystalline porous semiconductor electrodes, in full depletion conditions. Since band bending in a single colloidal particle is small, the idea is to develop a model that accounts for the total potential drop resulting from the equilibration between the Fermi level and the redox potential in the solution. As preliminary steps, the band bending and potential distribution in a planar electrode and also in a colloidal semiconductor particle are reviewed. In order to overcome the limitations of results based on these geometries, a model based on a columnar shape is developed. The Poisson equation is solved in the columnar electrode, with careful consideration of the boundary conditions. A large potential drop is shown to take place at the back contact. To complete the study, the effect of the depletion zone in the transparent conducting oxide is analysed. Simple expressions are derived that permit evaluation of how the total potential drop is distributed between the electrode and the substrate. From this, the strength and spatial range of the electric field in the electrode can be estimated.

High voltage MOSFET with geometrical depletion layer enhancement

Abstract: In a field-effect semiconductor device, for example a power MOSFET, a body portion separates a channel-accommodating region from a drain region at a surface of a semiconductor body. This body portion includes a drift region which serves for current flow of charge carriers of a first conductivity type from the conduction channel to the drain region, in a conducting mode of the device. Instead of being a single region, the body portion also includes field-relief regions of the second conductivity type, which are depleted together with the drift region in a voltage blocking mode of the device to provide a voltage-carrying space-charge region. The drain region extends at least partially around the body portion at the surface, and the relief regions are located radially in this body portion.

Secondary ion mass spectrometry study of space-charge formation in thermally poled fused silica

Abstract: Applying a dc electric field across a fused silica sample at elevated temperatures followed by cooling the sample with the field applied (thermal poling) leads to a second-order nonlinearity that has been linked to the formation of a space-charge region in bulk glass. The first microscopic information on the extent of the space-charge region and its behavior with poling time is reported using secondary ion mass spectrometry to monitor the distribution of charged impurities. Lithium and sodium ions are observed to form depletion regions. Potassium and sodium ions as well as a hydrogenated species appear to be injected from the surface. The extent of the space-charge region evolves approximately logarithmically with poling time well after the nonlinearity as measured by second-harmonic generation has been established. The evolution of the space charge region can be qualitatively understood by an ion-exchange model that allows interaction of two ionic carriers with vastly different mobilities.

Scanning capacitance microscope methodology for quantitative analysis of p-n junctions

Abstract: Quantification of dopant profiles in two dimensions (2D) for p-n junctions has proven to be a challenging problem. The scanning capacitance microscope (SCM) capability for p-n junction imaging has only been qualitatively demonstrated. No well-established physical model exists yet for the SCM data interpretation near the p-n junction. In this work, the experimental technique and conversion algorithm developed for nonjunction samples are applied to p-n junction quantification. To understand the SCM response in the active p-n junction region, an electrical model of the junction is proposed. Using one-dimensional secondary ion mass spectrometry (SIMS) data, the carrier distribution in the vertical dimension is calculated. The SIMS profile and carrier distribution is then compared with the SCM data converted using a first-order model. It is shown that for a certain class of profiles, the SCM converted dopant profile fits well to the SIMS data in one dimension. Under this condition, it is possible to identify the metallurgical p-n junction position in two dimensions. Examples of 2D metallurgical p-n junction delineation are presented. In addition, the SCM ability to locate the 2D position of the intrinsic point in the p-n junction depletion region is demonstrated. The SCM probe tip size is found to be a major factor limiting the SCM accuracy on shallow profiles. On junctions with shallow profiles, the SCM tip interacts with carriers on both sides of the junction. As a consequence, a decrease in accuracy and spatial resolution is observed using a first-order conversion algorithm.

Thermal poling of silica in air and under vacuum: the influence of charge transport on second harmonic generation

Abstract: A comparison between thermal poling of silica in air and in vacuum is reported. It is shown that the second-order susceptibility and thickness of the nonlinear layer as well as their time evolution are highly dependent on the surrounding poling atmosphere. In the vacuum case a charge distribution (under the anode) more complex and broader than that for the air case has also been revealed by laser induced pressure pulse measurements. A multiple charge carrier model can explain the formation and evolution of the depletion region under the anode. The findings are relevant to achieve improved nonlinearities in fiber and waveguide devices.

BUSFET-a radiation-hardened SOI transistor

Abstract: The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are 1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or 2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. We call this structure the BUSFET-Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source.

Photodiode and photodiode module

Abstract: Besides the central pn-junction and the central electrode, a PD chip has a peripheral pn-junction and a peripheral electrode which do not appear on the sides. The ends of the peripheral pn-junction are covered with a protection layer for preventing self-shortcircuit. A reverse bias is applied to the peripheral electrode for making a wide depletion layer beneath the peripheral pn-junction. Extra carriers generated by peripherally-incidence rays are fully absorbed by the peripheral depletion layer and annihilated by the reverse bias.

Methods of forming SOI insulator layers and methods of forming transistor devices

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region. The invention also includes a method comprising: a) providing a semiconductive substrate; b) forming a conductivity-modifying diffusion region in only a portion of the substrate; c) forming an insulator layer over the semiconductive substrate; d) forming a semiconductive layer over the insulator layer; e) forming a depletion region within the semiconductive layer, the depletion region being proximate the insulator layer and having a different thickness over the conductivity-modifying diffusion region than over other portions of the substrate; and f) etching the semiconductive layer to about the depletion region.

Radiation detection measurements with a new “Buried Junction” silicon avalanche photodiode

Abstract: An improved version of a recently developed “Buried Junction” avalanche photodiode (APD), designed for use with scintillators, is described and characterized. This device, also called the “Reverse APD”, is designed to have a wide depletion layer and thus low capacitance, but to have high gain only for e–h pairs generated within the first few microns of the depletion layer. Thus it has high gain for light from scintillators emitting in the 400–600 nm range, with relatively low dark current noise and it is relatively insensitive to minimum ionizing particles (MIPs). An additional feature is that the metallurgical junction is at the back of the wafer, leaving the front surface free to be coupled to a scintillator without fear of junction contamination. The modifications made in this device, as compared with the earlier diode, have resulted in a lower excess noise factor, lower dark current, and much-reduced trapping. The electrical and optical characteristics of this device are described and measurements of energy and timing resolution of this device with several scintillators (BGO, LSO and GSO) of potential interest in high-energy physics and PET imaging systems are presented.

Nanostructured semiconductor gas sensors to overcome sensitivity limitations due to percolation effects

Abstract: Semiconductor gas sensors are widespread in applications to detect toxic or explosive gases. Their gas-sensitive layer consists of a polycrystalline metal oxide film. The gas-detection principle is based on variations of the depletion layer at the grain boundaries in presence of reducing or oxidizing gases which leads to variations in the height of the energy barriers for free charge carriers (e.g. electrons in case of SnO2). The presence of a gas reduces the height of these barriers thus leading to an increased conductivity of the sensing material. The lower detection limit for gases is given by the fact that no (at least single) connected path exists between the reading electrodes below a certain gas concentration. The sensitivity of a gas sensor as well as its dynamic range can be improved significantly when nano technology methods are used to allow for parallel reading of shorter paths.

InP/InGaAs uni-travelling-carrier photodiode with 220 GHz bandwidth

Abstract: An InP/InGaAs uni-travelling-carrier photodiode with a record 3 dB bandwidth of 220 GHz at a wavelength of 1.55 µm has been fabricated. The estimated average electron velocity in the depletion region is > 2.3 × 107 cm/s, which indicates that non-equilibrium electron transport is taking place in the collection layer.

Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices

Abstract: As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction.

Leakage current behaviors of acceptor- and donor-doped (Ba0.5Sr0.5)TiO3 thin films

Abstract: We have investigated the effects of acceptor and donor doping on the leakage current behavior of Pt/(Ba0.5Sr0.5)TiO3/Pt film capacitors prepared by a pulsed-laser deposition method. We selected Mn/Al and Nb as acceptor and donor dopants, respectively. The leakage current behavior depends strongly on the type of dopants. Al doping decreases the leakage current level, and Mn doping decreases it further. Nb doping greatly increases it. The decrease in leakage current associated with acceptor doping seems to partly result from a decrease in tunneling current due to expansion of the depletion layer width. The converse appears to apply with donor doping.

n-type control by sulfur ion implantation in homoepitaxial diamond films grown by chemical vapor deposition

Abstract: n-type control was achieved by sulfur-ion-implantation in homoepitaxial diamond (100) films grown by chemical vapor deposition (CVD) for the first time. Sulfur-implantation was carried out with energies of up to 400 keV at 400°C. The activation energy of the conductivity was 0.19–0.33 eV depending on the conditions of ion implantation. A junction between this layer and a boron-doped p-type layer was fabricated by combining sulfur-implantation with gas-phase boron doping during CVD. The junction exhibited clear pn junction properties. The capacitance of the junction decreased with reverse bias voltage, which confirms that the depletion region of the junction was actually extended with the reverse bias voltage.

Analysis of deep levels in a phenylenevinylene polymer by transient capacitance methods

Abstract: Transient capacitance methods were applied to the depletion region of an abrupt asymmetric n+−p junction of silicon and unintentionally doped poly[2-methoxy, 5 ethyl (2′ hexyloxy) paraphenylenevinylene] (MEH-PPV). Studies in the temperature range 100–300 K show the presence of a majority-carrier trap at 1.0 eV and two minority traps at 0.7 and 1.3 eV, respectively. There is an indication for more levels for which the activation energy could not be determined. Furthermore, admittance data reveal a bulk activation energy for conduction of 0.12 eV, suggesting the presence of an additional shallow acceptor state.

Investigation of the Electronic Properties of Organic Light-Emitting Devices by Impedance Spectroscopy

Abstract: A key for the understanding of the electronic properties of organic light-emitting devices (OLEDs) is the frequency dependent investigation of their complex resistance. We report impedance spectroscopy measurements of electroluminescent (EL) single-layer and double-layer systems. It is shown that there are important differences found in the corresponding equivalent electrical circuits. In EL single-layer devices the electrical field decreases homogeneously over the entire layer thickness, resulting in an equivalent circuit of one RC component. In contrast, for the EL two-layer devices two RC components are necessary for the description. In both systems no indications of an insulating layer or a depletion region are found. During the measurements of the impedances of operated EL single-layer and EL two-layer systems, both under inert gas and in air, an increase of the resistance is observed. However, there are no signs for an insulating layer covering the entire contact area, through which the transport of...

Effect of quantum well location on single quantum well p-i-n photodiode dark currents

Abstract: The photocurrent available from a p-i-n solar cell can be increased by the addition of quantum wells (QWs) to the undoped region. At the same time the QWs reduce the open-circuit voltage by introducing areas of lower band gap where recombination is enhanced. This increase in recombination should be as small as possible for the most favorable effect on the photovoltaic efficiency of the device. Theoretical considerations indicate that nonradiative recombination, which is the dominant loss mechanism in AlxGa1−xAs/GaAs QW structures, may be reduced by positioning the QWs away from the point where the electron-hole product is a maximum. For p-i-n diodes, where recombination is greatest at or near the center of the space charge region, this means locating the QWs closer to the doped regions. Spectral response should not be affected so long as the QWs are still located within the field bearing region. Thus, improved photovoltaic performance may be expected through strategic location of the QWs. We report on measurements on a series of Al0.36Ga0.64As p-i-n photodiodes, three of which contained a single 87 A GaAs QW within the i region, and one which was a control sample with no QW. The three QW samples were grown with the QW located nearer to the p-doped layer, centrally, and nearer to the n-doped layer, respectively. Spectral response measurements confirm that for good quality samples photocurrent is independent of QW location within the depleted region. Contrary to expectations, the dark current is highest for the sample with the QW located closer to the n region. We analyze these results in terms of structure and doping profile, and compare them with the predictions of a self-consistent model. The observed behavior is attributed to a relatively high unintentional background doping in the intrinsic region.

Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture

Abstract: Fringing fields into the buried oxide and substrate depletion region stand as a key limiting factor for SOI MOSFET channel length reduction beyond 0.1 /spl mu/m. In fully-depleted (FD) SOI transistors, they cause a strong DIBL enhancement and a parasitic back channel conduction. On the other hand, in partially-depleted (PD) devices, the back channel control is even more difficult. The understanding and modeling of this phenomenon is of major interest, especially for RF SOI applications on high resistivity substrates where the depleted substrates behave as dielectrics. Various solutions to reduce these drawbacks are envisaged, such as buried oxide shrinking or double gate devices (Colinge, 1997; Cristoloveanu and Li, 1995). Thus far, the fringing field effect was ignored or merely included in FD analytical models by use of adjustable parameters. This paper presents a simple physical model for the evaluation of short channel effects induced by the BOX and substrate depletion. We analyze the lateral drain field penetration in the BOX and substrate, and calculate the related fringing capacitances. The model serves to anticipate the buried oxide scaling and substrate resistivity effects and to suggest the "ground plane" (GP) concept (Ernst and Cristoloveanu, 1999; Wong et al, 1998) as a suitable architecture for deep sub-micron SOI MOSFETs.

Linear capacitor structure in a CMOS process

Abstract: A cumulative capacitor structure with desirably constant capacitance characteristics is disclosed. In one embodiment, the cumulative capacitor includes a set of four capacitors coupled in parallel between first and second terminals of the cumulative capacitor. In one embodiment, the first capacitor is comprised of a top plate formed of an n-type polysilicon coupled to the first terminal, a bottom plate comprised of a first accumulation/depletion region such as an n-well region coupled to the second terminal, and a first dielectric region between its top and bottom plates. The second capacitor has an n-type polysilicon terminal top plate coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plate. A third capacitor has a p-type polysilicon top plate coupled to the first terminal, an accumulation/depletion region bottom plate coupled to the second terminal, and a third dielectric region between its top and bottom plates. The fourth capacitor has a p-type polysilicon terminal coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plates.

Reduction of the base-collector capacitance in InP/GaInAs heterojunction bipolar transistors due to electron velocity modulation

Abstract: The base-collector capacitance of an InP/GaInAs heterojunction bipolar transistor (HBT) was measured as a function of collector current and base-collector voltage The experimentally obtained results were considerably smaller than the expected dielectric capacitance For example, at a collector current density of 50 kA/cm/sup 2/ the value of the intrinsic C/sub bc/ was 33% less than the expected dielectric capacitance A model that takes into account modulation of electron velocity in the collector depletion region by the base-collector voltage was employed to account for the experimental results An arbitrary profile of the electron velocity in the collector, which accounts for the velocity overshoot effect, was assumed in developing this model Excellent agreement was obtained with no fitting parameters The model relates the change in C/sub bc/ to the variation of the collector delay time with base-collector voltage

Photodiode having charge transfer function and image sensor using the same

Abstract: The present invention relates to an image sensor; and, more particularly, to a CMOS image sensor employing photodiodes which linearly increase the ability of keeping up photogenerated charges. In accordance with the present invention, a unit pixel of a CMOS image sensor comprises: a photodiode including: a) an N-type semiconductor region and a P-type semiconductor region for a PN junction to which a reverse bias is applied; and b) a highly doped region formed on one of the N-type semiconductor region and the P-type semiconductor region for collecting carriers of electron-hole pairs generated in a depletion region of the PN junction so that a voltage drop of the reverse bias is linear; and an image data processing unit for producing an image data in response to the carriers transferred from the highly doped region.

Vertical field-effect semiconductor device with buried gate region

Abstract: A buried gate region, a buried gate contact region and a gate contact region are provided on an SiC substrate. Thereby, a depletion layer expands in the channel region, and a high withstand voltage is attained in the normally off state. By applying a voltage of the built-in voltage or less to a gate, the depletion layer in the channel region becomes narrower and an ON-state resistance becomes low. Furthermore, when a voltage of the built-in voltage or more is applied to the gate, holes are injected from the gate so as to cause the conductivity modulation, and the ON-state resistance becomes further low.

Methods and apparatus for a composite collector double heterojunction bipolar transistor

Abstract: A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.

CMOS versus bipolar Hall plates regarding offset correction

Abstract: Integrated silicon Hall devices are used to measure magnetic fields. Unfortunately, they cannot be used in low field applications because they suffer from a large, unpredictable and drifting offset. Using the spinning-current method the offset can be reduced to a few microtesla, which enables low field applications. This paper reports on the influence of the fabrication process, CMOS or bipolar, on the offset of spinning-current Hall plates. The depletion layer width of the junction that defines the boundaries of the Hall plate, which is different for the two fabrication processes, influences the sensitivity, resistance, and offset of integrated Hall plates. Theoretical studies can predict the sensitivity and resistance, but not the offset. The depletion layer width depends on the bias current and the substrate voltage. To study the influence of the depletion layer width on the Hall plates' characteristics these two parameters are varied. Experiments show that the spinning-current principle drastically reduces the offset, independent of the bias current and substrate voltage, and therefore independent of the depletion layer width and fabrication method.

Avalanche photodiode with thin built-in depletion region

Abstract: The present invention relates to an avalanche photodiode having a simple structure, high reliability, and a high speed response on the order of Gbps. This photodiode is formed by depositing laminated layers on a semiconductor substrate in the order of an n-type buffer layer, a semiconductor multiplication layer, a p-type semiconductor field buffer layer, a p-type semiconductor light absorbing layer, a p-type semiconductor cap layer, and a p-type semiconductor contact layer, and said p-type semiconductor light absorbing layer is constructed by two layers consisted of a depleted region of a thickness in the range of 10 nm to 0.3 μm disposed adjacent to the p-type semiconductor field buffer layer and a non-depleted layer region at a thickness of less than 2 μm disposed adjacent to the depleted layer region.