Depletion region

About: Depletion region is a research topic. Over the lifetime, 9393 publications have been published within this topic receiving 145633 citations.

Method of manufacturing a CMOS device

Abstract: of EP0683515In a method for improving characteristics of a CMOS, the CMOS includes first and second wells (18,22) formed in first and second regions of a semiconductor substrate (10), respectively, first and second transistors formed on the respective wells, a third transistor formed in a third region of the semiconductor substrate, a first impurity layer (100) formed in the vicinity of the depletion region of at least one region among the first to third regions for a transistor requiring a high punch-through voltage, and a second impurity layer (101) deeper than the first impurity layer and formed in the semiconductor substrate of the or each region where the first impurity layer is not formed for a transistor not requiring a high punch-through voltage and thus having an operating voltage that is not affected by back bias. Therefore, characteristics of the transistors formed in a well and/or substrate can be selectively sufficed without a separate mask process.

Analysis of Recombination Mechanisms in RbF-Treated CIGS Solar Cells

Abstract: In this paper, we studied the effect of rubidium fluoride (RbF) post-deposition treatment (PDT) on the properties of Cu(In,Ga)Se2 (CIGS) solar cells. Specifically, the recombination mechanisms were analyzed by a series of characterizations including thermal and optical defect spectroscopies, temperature dependent current density–voltage measurements, and time resolved photoluminescence. It was found that the main effect of RbF PDT on the solar cell was an increase of the open circuit-voltage, $V_{{\text{oc}}}$ , by 30 mV due to a decrease of the values of the diode quality factor and reverse saturation current. Recombination mechanisms were identified as being in the CIGS space charge region, likely at the grain boundaries and near the CIGS surface. Breakdown of contributions to the $V_{{\text{oc}}}$ increase showed that part of it is due to an increase of the majority carrier concentration (16 mV) and another to the increase in the minority carrier lifetime (1 mV). The latest is mostly due to a reduction in the EV+0.99 eV deep-level trap density. An additional CIGS surface modification (contributing 13 mV), observed by the secondary ion mass spectrometry, is essential to explain the full change in $V_{{\text{oc}}}$ .

Current mode second breakdown in epitaxial planar transistors

Abstract: Current mode second breakdown is a type of voltage "switchback" observed in epitaxial transistors. The phenomenon is initiated when the emitter is injecting at a collector voltage in excess of the collector-emitter sustaining voltage, and is characterized by delay and voltage fall times on the order of a nanosecond. The device can be sustained in the low voltage state only as long as there is sufficient charge to produce conductivity modulation within the collector-base depletion region. When the available charge is exhausted, the collector voltage will recharge at a rate determined by the external circuit. At some critical current density, the collector-base depletion region collapses toward the high conductivity substrate. The electric field within the depletion region increases as the depletion region width narrows, until avalanche occurs. The sustaining voltage will be determined by the bulk base-to-collector avalanche voltage. A consequence of this behavior is that most epitaxial transistors cannot operate stably in the LV CER mode, and switching-off unclamped inductive circuits with the emitter-base junction terminated in some finite resistance will lead to second breakdown.

Optimization of BF2+ implanted and rapidly annealed junctions in silicon

Abstract: The electrical properties and defect characteristics of shallow junctions fabricated by using BF2+‐ion implantation and followed by either furnace or rapid thermal annealing (RTA) have been investigated. The RTA temperature‐time cycle was optimized in terms of leakage current, junction depth, and sheet resistivity of junctions. Specifically, shallow p+ junctions (∼180 nm) with low leakage current (∼2 nA/cm2 at −5 V) were obtained with 49‐keV, 2×1015‐cm−2 BF2+ implantation and RTA at 1050 °C for 15 s. The effects of a Si+ preamorphizing implant and pre‐ or post‐RTA low‐temperature furnace anneal were also studied. p+/n diodes fabricated with a preamorphizing implantation exhibit about 3 orders of magnitude higher leakage current than the diodes without preimplantation. The excessive leakage current of the preamorphized junctions arises from a band of post‐annealing defects located in the depletion region of the n well (from ∼220 to 420 nm). Samples without the Si+ implant have very shallow and narrow defec...