Depletion region

About: Depletion region is a research topic. Over the lifetime, 9393 publications have been published within this topic receiving 145633 citations.

Microwave noise performance of InP/InGaAs heterostructure bipolar transistors

Abstract: The authors report the first low-noise InP/InGaAs heterostructure bipolar transistor (HBT). Minimum noise figures of 0.46, 2.0, and 3.33 dB were measured at 2, 10, and 18 GHz, respectively. The noise performance of this InP/InGaAs HBT with an emitter size of 3.5*3.5 mu m/sup 2/ is compared to that for FETs having a 1- mu m gate length. The measured minimum noise figures agree well with calculated data using a modified Hawkins model. Broadband low-noise operation is observed because of the short transit time for injected nonequilibrium electrons to transverse the base and collector depletion region. >

Implications of radiation-induced dopant deactivation for npn bipolar junction transistors

Abstract: Metal-oxide-silicon capacitors fabricated in a bipolar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100/spl deg/C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H/sup +/ ions in the oxide and Si layers and the availability of holes in the Si depletion region. The capacitor data were used to simulate the impact of acceptor neutralization on the current gain of an irradiated npn bipolar transistor. Neutralized accepters near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may complicate hardness assurance test methods for linear circuits, which are based on elevated temperature irradiations.

Photodiode having charge transfer function and image sensor using the same

Abstract: The present invention relates to an image sensor; and, more particularly, to a CMOS image sensor employing photodiodes which linearly increase the ability of keeping up photogenerated charges. In accordance with the present invention, a unit pixel of a CMOS image sensor comprises: a photodiode including: a) an N-type semiconductor region and a P-type semiconductor region for a PN junction to which a reverse bias is applied; and b) a highly doped region formed on one of the N-type semiconductor region and the P-type semiconductor region for collecting carriers of electron-hole pairs generated in a depletion region of the PN junction so that a voltage drop of the reverse bias is linear; and an image data processing unit for producing an image data in response to the carriers transferred from the highly doped region.

Behavior of a rectifying junction at the interface between porous silicon and its substrate

Abstract: The current injection into metal/porous Si/bulk Si diodes is investigated by transport and photoresponse measurements. Under low forward bias, the diode current is determined by the space charge region at the porous Si/bulk Si interface. The activation energy of the photovoltage shows that holes are injected into porous Si states which have little quantum confinement. This is discussed in terms of the confinement model for porous Si photoluminescence.

Photonic Transitions (1.4 eV–2.8 eV) in Silicon p $^{+}$ np $^{+}$ Injection-Avalanche CMOS LEDs as Function of Depletion Layer Profiling and Defect Engineering

Abstract: p+np+ CMOS Si LED structures were modeled in order to investigate the effect of various depletion layer profiles and defect engineering on the photonic transitions in the 1.4-2.8 eV, 450-750 nm regime. Modeling shows that by utilizing a short linear increasing E-field in the p+n reverse-biased junction with a gradient of approximately 5 × 105 V cm-1· ?m-1, and injecting carriers from an adjacent p+n junction, increased localized optical yield by a factor 50-100. A number of device designs were realized using CMOS 0.35 ?m technology. The device design involves normal CMOS design and processing procedures with no excessive microdimensioning. The current devices operated in the 6-8 V, 1 ?A-2 mA regime, and yield emission intensities of up to 100 nW ?m-2. The current emission levels are about three orders higher than the low-frequency detectability limit of Si CMOS p-n detectors of corresponding area, which make diverse electro-optical applications such as MOEMS devices, and diverse optical signal processing and wave-guiding and the development of ?smart chips? feasible in standard CMOS integrated circuitry.