Depletion region

About: Depletion region is a research topic. Over the lifetime, 9393 publications have been published within this topic receiving 145633 citations.

Reducing high-frequency signal loss in substrates

Abstract: An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region.

A capacitorless dram device on silicon-on-insulator substrate

Abstract: A DRAM device has a first semiconductor region (18) of one conductivity on the silicon film of a silicon-on-insulator substrate (22). A second (16) and a third (14) semiconductor region of the opposite conductivity are formed in the first semiconductor region (18). A fourth semiconductor region (12) of the same conductivity type as the first semiconductor region (18) is formed within the second semiconductor region (16) with higher doping concentration. A insulating layer (11) is formed on the semiconductor surface. On top of the insulating layer (11), a gate electrode (10) is formed and is at least partially overlapped with the first (18), the second (16), the third (14), and the fourth (12) semiconductor region. A storage node (24) is formed in the first semiconductor region (18) between the second (16) and the third (14) semiconductor region where the information is stored. The amount of charge stored in the storage node (24) is controlled by a first transistor including the fourth semiconductor region (12), the second semiconductor region (16), the storage node (24), and the gate electrode (10).

Incompatible Length Scales in Nanostructured Cu2O Solar Cells

Abstract: Electrodeposited Cu2O-ZnO heterojunctions are promising low-cost solar cells. While nanostructured architectures improve charge collection in these devices, low open-circuit voltages result. Bilayer and nanowire Cu2O-ZnO heterojunction architectures are systematically studied as a function of the Cu2O layer thickness, ZnO nanowire length, and nanowire seed layer. It is shown that a thick depletion layer exists in the Cu2O layer of bilayer devices, owing to the low carrier density of electrodeposited Cu2O, such that the predominant charge transport mechanisms in the Cu2O and ZnO are drift and diffusion, respectively. This suggests that the low open-circuit voltage of the nanowire cells is due to an incompatibility between the nanostructure spacing required for good charge collection ( 2 μm). The work shows the way to improve low-cost Cu2O cells: increasing the carrier concentration or mobility in Cu2O synthesized at low temperatures.

Depletion Layers and Domain Walls in Semiconducting Ferroelectric Thin Films

Abstract: Commonly used ferroelectric perovskites are also wide-band-gap semiconductors. In such materials, the polarization and the space-charge distribution are intimately coupled, and this Letter studies them simultaneously with no a priori ansatz on either. In particular, we study the structure of domain walls and the depletion layers that form at the metal-ferroelectric interfaces. We find the coupling between polarization and space charges leads to the formation of charge double layers at the 90° domain walls, which, like the depletion layers, are also decorated by defects like oxygen vacancies. In contrast, the 180° domain walls do not interact with the defects or space charges. Implications of these results to domain switching and fatigue in ferroelectric devices are discussed.