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Depletion region

About: Depletion region is a research topic. Over the lifetime, 9393 publications have been published within this topic receiving 145633 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, a non-conventional JFET (junction field effect transistor), designed to operate on a completely depleted, 2-k Omega -cm resistivity silicon substrate, has been designed, fabricated, and tested at room temperature.
Abstract: To satisfy the increasing interest in the integration of electronics onto optical and ionizing particle fully depleted detectors, a nonconventional JFET (junction field-effect transistor), designed to operate on a completely depleted, 2-k Omega -cm resistivity silicon substrate, has been designed, fabricated, and tested at room temperature. The devices show very low gate leakage current, low output conductance, a transconductance per unit gate width of 3 mS/mm, and a pinch-off voltage of -1.5 V. The integration of the devices onto the detectors makes possible the matching of the input capacitance of the JFET to the detector's output capacitance, which is of the order of few hundreds of femtorads. The measured gate capacitance of 200 fF is shown to correspond to an expected resolution in charge measurements, at room temperature, of less than 40 electrons rms. The fabrication constraints, imposed by the limited number of production steps of the detectors, are reported. >

110 citations

Journal ArticleDOI
TL;DR: In this paper, a back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD) was implemented in 45-nm CMOS technology for the first time.
Abstract: We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P+/Deep N-well junction with a circular shape, for which N-well is intentionally excluded to achieve a wide depletion region, thus enabling lower tunneling noise and better timing jitter as well as a higher photon detection efficiency and a wider spectrum. In order to prevent premature edge breakdown, a P-type guard ring is formed at the edge of the junction, and it is optimized to achieve a wider photon-sensitive area. In addition, metal-1 is used as a light reflector to improve the detection efficiency further in backside illumination. With the optimized 3-D stacked 45-nm CMOS technology for back-illuminated image sensors, the proposed SPAD achieves a dark count rate of 55.4 cps/μm2 and a photon detection probability of 31.8% at 600 nm and over 5% in the 420–920 nm wavelength range. The jitter is 107.7 ps full width at half-maximum with negligible exponential diffusion tail at 2.5 V excess bias voltage at room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3-D stacked SPAD technologies.

110 citations

Patent
David D. Smith1
29 Apr 2009
TL;DR: In this article, a trench structure is proposed to separate polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer.
Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.

110 citations

Journal ArticleDOI
TL;DR: An electrochemical quartz crystal impedance system (EQCIS) was used to investigate depletion layer effects on equivalent circuit parameters of piezoelectric quartz crystal resonance in electrochemi.
Abstract: An electrochemical quartz crystal impedance system (EQCIS) was used to investigate depletion layer effects on equivalent circuit parameters of piezoelectric quartz crystal resonance in electrochemi

109 citations

Journal ArticleDOI
TL;DR: Electronic transport measurements in individual Au-catalyst/Ge-nanowire interfaces demonstrating the presence of a Schottky barrier are presented and the small-bias conductance density increases with decreasing diameter.
Abstract: We present electronic transport measurements in individual Au-catalyst/Ge-nanowire interfaces demonstrating the presence of a Schottky barrier. Surprisingly, the small-bias conductance density increases with decreasing diameter. Theoretical calculations suggest that this effect arises because electron-hole recombination in the depletion region is the dominant charge transport mechanism, with a diameter dependence of both the depletion width and the electron-hole recombination time. The recombination time is dominated by surface contributions and depends linearly on the nanowire diameter.

109 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202326
202266
2021151
2020198
2019229
2018239