Depletion region

About: Depletion region is a research topic. Over the lifetime, 9393 publications have been published within this topic receiving 145633 citations.

Potential-Induced Degradation (PID): Introduction of a Novel Test Approach and Explanation of Increased Depletion Region Recombination

Abstract: In recent years, a detrimental degradation mechanism of solar cells in large photovoltaic fields called potential-induced degradation (PID) has been intensively investigated and discussed. Here, the module efficiency is decreasing down to a fractional part of their original efficiency. In this study, we introduce a PID test at a solar-cell level and for individual module components applicable as a tool for process control in industries and root cause analyses in science departments. Using the proposed method, one example analysis of a solar cell that is degraded by the PID tester is presented. It is shown that PID of the shunting type influences both the parallel resistance (Rp) and the depletion region recombination behavior (J02) of the solar cell. Increased recombination in the depletion region is caused by Na decorated stacking faults crossing the depletion region. This strongly influences recombination behavior in the depletion region, leading to an increased J02 and an ideality factor n2 > 2. However, the defects leave the base of the solar cell primarily unaffected, and hence, J01 recombination remains rather low. Based on these findings, a model for the shunting and the increased depletion region recombination behavior is discussed.

Nonvolatile bipolar resistive switching in Au/BiFeO3/Pt

Abstract: Nonvolatile bipolar resistive switching has been observed in an Au/BiFeO3/Pt structure, where a Schottky contact and a quasi-Ohmic contact were formed at the Au/BiFeO3 and BiFeO3/Pt interface, respectively. By changing the polarity of the external voltage, the Au/BiFeO3/Pt is switched between two stable resistance states without an electroforming process. The resistance ratio is larger than two orders of magnitude. The resistive switching is understood by the electric field - induced carriers trapping and detrapping, which changes the depletion layer thickness at the Au/BiFeO3 interface.

MOS field effect transistor and its manufacturing method

Abstract: A method of manufacturing a MOS field effect transistor comprises forming on a semiconductor substrate a first epitaxial growth layer having an impurity doping concentration lower than that of the semiconductor substrate, forming on the first epitaxial growth layer a second epitaxial growth layer having an impurity concentration higher than that of the first epitaxial growth layer and having a thickness equal to or less than a diffusion depth of a source and a drain region, and forming on the second eptiaxial growth layer a third epitaxial growth layer having an impurity concentration lower than that of the second epitaxial growth layer and having a thickness equal to or less than that of a depletion layer at a channel region.

Semiconductor device and method of manufacturing semiconductor device

Abstract: A semiconductor device includes a first-first conductivity type semiconductor layer which includes a cell region portion and a junction terminating region portion, the junction terminating region portion being a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field; a second first conductivity type semiconductor layer which is formed on one surface of the first-first conductivity type semiconductor layer; a first main electrode which is electrically connected to the second-first conductivity type semiconductor layer; first-second conductivity type semiconductor layers which are formed in the cell region portion of the first-first conductivity type semiconductor layer in substantially vertical directions to the one surface of the first-first conductivity type semiconductor layer, respectively, and which are periodically disposed in a first direction which is an arbitrary direction parallel to the one surface; a second-second conductivity type semiconductor layer which is selectively formed in the other surface portion of the first-first conductivity type semiconductor layer so as to contact the first-second conductivity type semiconductor layers; a third-first conductivity type semiconductor layer which is selectively formed in the surface portion of the second-second conductivity type semiconductor layer; a second main electrode which is formed so as to contact the second-second conductivity type semiconductor layer and the third first conductivity type semiconductor layer; a control electrode which is formed on the surface of the first-first conductivity type semiconductor layer sandwiched by the adjacent second-second conductivity type semiconductor layers, the surface of the adjacent second-second conductivity type semiconductor layers and the surface of the third-first conductivity type semiconductor layer, with a gate insulating film interposed therebetween; and third-second conductivity type semiconductor layers which are formed in the junction terminating region portion and are periodically disposed in at least one direction of the first direction and a second direction perpendicular to the first direction