Depletion region

About: Depletion region is a research topic. Over the lifetime, 9393 publications have been published within this topic receiving 145633 citations.

Induced electrokinetic transport in micro-nanofluidic interconnect devices.

Abstract: Hybrid micro-nanofluidic interconnect devices can be used to control analyte transfer from one microchannel to the other through a nanochannel under rest, injection, and recovery stages of operation by varying the applied potential bias. Using numerical simulations based on coupled transient Poisson-Nernst-Planck and Stokes equations, we examine the electrokinetic transport in a gateable device consisting of two 100 microm long, 1 microm wide negatively charged microchannels connected by a 1 microm long, 10 nm wide positively charged nanochannel under both positive and negative bias potentials. During injection, accumulation of ions is observed at the micro-nano interface region with the positive potential and depletion of ions is observed at the other micro-nano junction region. Net space charge in the depletion region gives rise to nonlinear electrokinetic transport during the recovery stage due to induced pressure, induced electroosmotic flow of the second kind, and complex flow circulations. Ionic currents are computed as a function of time for both positive and negative bias potentials for the three stages. Analytical expressions derived for ion current variation are in agreement with the simulated results. In the presence of multiple accumulation or depletion regions, we show that a hybrid micro-nano device can be designed to function as a logic gate.

SOI FET design to reduce transient bipolar current

Abstract: Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor formed therewith to be transiently reduced and the effective base-emitter junction capacitance to be transiently increased during only modes of operation in which the parasitic bipolar conduction dominates normal operation of the field effect transistor. Such transient reduction of gain coupled with a transient reduction of high frequency response reduces the parasitic bipolar current spike to a degree greater than previously achievable and is fully compatible with other techniques of reducing such current spike. As applied to an SOICMOS SRAM, the transistor structure including such a gap is effective in suppressing half-select write disturb effects while maintaining the benefits of excess charge storage and floating body effects in the transistor.

High voltage MOSFET with geometrical depletion layer enhancement

Abstract: In a field-effect semiconductor device, for example a power MOSFET, a body portion separates a channel-accommodating region from a drain region at a surface of a semiconductor body. This body portion includes a drift region which serves for current flow of charge carriers of a first conductivity type from the conduction channel to the drain region, in a conducting mode of the device. Instead of being a single region, the body portion also includes field-relief regions of the second conductivity type, which are depleted together with the drift region in a voltage blocking mode of the device to provide a voltage-carrying space-charge region. The drain region extends at least partially around the body portion at the surface, and the relief regions are located radially in this body portion.

Junction termination extension for near-ideal breakdown voltage in p-n junctions

Abstract: Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implanted junction extension for precise control of the depletion region charge in the junction termination. A theory is presented that shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, plane-junction moat-etch-terminated diodes with a normal breakdown voltage of 1050 V and a 0.5-mA leakage current become 1400 V (1450 ideal) devices with a 5-µA leakage current. Planar junctions, which broke down at 300 V, blocked as much as 1400 V if JTE terminated. Since planar junctions are of the greatest interest, we incorporated multiple field ring, field plate, and JTE terminations on a mask set and fabricated and tested thousands of devices. The results clearly showed that the ideal breakdown voltage can be achieved with less than 200 µm with JTE, where the same area would lead to 30 to 45 percent of the ideal with field rings and up to 40 to 50 percent of the ideal when used with field rings combined with field plates. Eight rings, even combined with a field plate, yielded less than 80 percent of the ideal breakdown voltage and required about 400 µm of device periphery.