Depletion region

About: Depletion region is a research topic. Over the lifetime, 9393 publications have been published within this topic receiving 145633 citations.

Erasable, programmable read-only memory device

Abstract: An erasable, programmable read-only memory device comprises a plurality of memory cells of channel injection type. First and second impurity regions used as source and drain have different configurations such that when the same level of voltages are applied to first and second impurity regions, respectively, the intensity of electric field near the channel region in the depletion layer between the second impurity region and the substrate is weaker than that in the depletion layer between the first impurity region and the substrate. In the writing operation, a higher voltage in absolute value is applied to the first impurity region and channel current flows in one direction. Therefore, hot electrons can be effectively injected into the floating gate near the first impurity region. On the other hand in the reading operation, a higher voltage in absolute value is applied to the second impurity region and channel current flows in the opposite direction. The voltage in the reading operation is lower in absolute value than the voltage in the writing operation. According to such a device, the unintentional injection writing phenomenon in the reading operation can be suppressed.

High-frequency performance limitations of millimeter-wave heterojunction bipolar transistors

Abstract: Heterojunction bipolar transistor structure (HBTs) with 0.25-, 0.4-, and 0.6- mu m emitter stripe widths and ultrasubmicrometer base widths, which are designed to achieve minimum transit time and low parasitic effects, are examined for their millimeter-wave performance. In particular,the dependence of the unity current gain frequency (f/sub tau /), the maximum oscillation frequency (f/sub max/), and the stability of power gains on the device structure and material parameters are critically analyzed. It is shown that the classical f/sub max/ expression commonly used for bipolar transistors, involving the effective carrier transit time and the collector-based RC time constant does not adequately represent the performance of ultrasubmicrometer-based-width HBTs, where the transadmittance phase delay associated with the collector-base depletion layer transit time and the parasitic collector-based capacitance are significant. The expected ballistic and quasiballistic behaviour of electron in these ultrasubmicrometer structures, if properly designed, minimizes the effective carrier transit time effect, but its impact on the f/sub max/ by the excess transadmittance phase delay poses a more fundamental and serious high-frequency limiting factor for the realization of millimeter-wave HBTs than has been hitherto recognized. The accuracy and usefulness of the proposed analytical approach is demonstrated for a practical HBT structure with 1.2- mu m emitter stripe design, giving results that agree well with measurements. >

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To enable a semiconductor device to be lessened in electrostatic capacity between a gate and a drain and enhanced in high frequency characteristics without providing a groove or the like. CONSTITUTION:A buried oxide layer (SiO2 layer) 20 low in permittivity is selectively formed under a P -type gate region 4 coming into contact with it. At this point, the buried oxide layer 20 is formed through a SIMOX method. In this constitution, even if a depletion layer 9 expands to make a semiconductor device of this design pinched off, the depletion layer 9 formed around a gate region 4 only expands partially below the gate electrode 7 because the buried oxide layer 20 is provided under the gate region 4, whereby the semiconductor device of this design can reduce electrostatic capacity between a gate 7 and a drain 8.

Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology

Abstract: The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900 degrees C/30 min to rapid thermal annealing at 1050 degrees C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G/sub m/ of NMOS transistors with 125-AA Gate oxide thickness.