Depletion region

About: Depletion region is a research topic. Over the lifetime, 9393 publications have been published within this topic receiving 145633 citations.

Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance

Abstract: A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second conductivity type formed in the body region. A portion of the body region adjacent to the source region is compensated by ion implanting a material of the second conductivity type in the portion of the body region such that the impurity concentration of the body region at the portion is reduced. As a consequence, with reduced impurity charge in the body region adjacent to the source, the threshold voltage of the MOSFET device is lowered but at no comprise in punch-through tolerance because the reduction in charge is remote from the origin of the depletion layer which is located at the boundary between the body region and the epitaxial layer.

N-polar III-nitride quantum well light-emitting diodes with polarization-induced doping

Abstract: Nitrogen-polar III-nitride heterostructures present unexplored advantages over Ga(metal)-polar crystals for optoelectronic devices. This work reports N-polar III-nitride quantum-well ultraviolet light-emitting diodes grown by plasma-assisted molecular beam epitaxy that integrate polarization-induced p-type doping by compositional grading from GaN to AlGaN along N-face. The graded AlGaN layer simultaneously acts as an electron blocking layer while facilitating smooth injection of holes into the active region, while the built-in electric field in the barriers improves carrier injection into quantum wells. The enhanced doping, carrier injection, and light extraction indicate that N-polar structures have the potential to exceed the performance of metal-polar ultraviolet light-emitting diodes.

Thermally poled silica glass: Laser induced pressure pulse probe of charge distribution

Abstract: Charge distributions in thermally poled silica glass are mapped by using laser induced pressure pulse technique. The experimental results may be explained through postulating the formation of both real space charge layers and dipole polarization inside the depletion region.

Surface State and Interface Effects on the Capacitance‐Voltage Relationship in Schottky Barriers

Abstract: In the presence of an interfacial layer and semiconductor surface states, a Schottky barrier height φb decreases with increasing electric field E at the surface of the semiconductor. If the semiconductor doping concentration Nd is uniform throughout the depletion region and if [ (qNd/e) (dφb/dE)−E] [ (d2φb/dE2) (dE/dV) ]≪1, where V is the applied voltage and e is the semiconductor permittivity, the slope of the (capacitance)−2 vs voltage relationship is constant and can be interpreted to give Nd. The voltage intercept of the relationship yields an apparent barrier height φa related to the true barrier φb by φa=φb−E (dφb/dE) + (qNd/2e) (dφb/dE)2, where q is the electron charge. From the measured variation of φa with Nd and one absolute measure of φb at one value of Nd, φb(E), and dφb(E)/dE may be deduced. From dφb(E)/dE the surface state density as a function of energy in the bandgap and the minimum value of interface thickness divided by relative interface permittivity can be obtained. Using the data of Archer and Atalla for vacuum cleaved Au‐Si diodes to illustrate our method, the surface state density is found to peak at a value of ∼2×1014 cm−2·eV−1 at about 0.83 below the conduction band and the minimum value of interface thickness divided by relative dielectric constant is found to be of the order of 5 A. Criteria are given which show how Schottky diode capacitance‐voltage data may be further used, in conjunction with photoelectric barrier measurements, to detect the presence of deep lying impurities or the penetration of surface state charge into the body of the semiconductor.

New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI

Abstract: A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI) Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced Moreover, the Si window alleviates the self-heating effect The influences of the structure parameters on device characteristics are analyzed for the proposed device structure The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of EI > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 87 K in comparison with the conventional SOI and partial SOI devices