Design for testing
About: Design for testing is a(n) research topic. Over the lifetime, 3946 publication(s) have been published within this topic receiving 63049 citation(s). The topic is also known as: Design for Testability, DFT.
Papers published on a yearly basis
07 Apr 2013
TL;DR: This book provides a careful selection of essential topics on all three types of circuits, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods.
Abstract: Today's electronic design and test engineers deal with several types of subsystems, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods. This book provides a careful selection of essential topics on all three types of circuits. The outcome of testing is product quality, which means "meeting the user's needs at a minimum cost". The book includes test economics and techniques for determining the defect level of VLSI chips. Besides being a textbook for a course on testing, it is a complete testability guide for an engineer working on any kind of electronic device or system or a system-on-a-chip.
01 Feb 2005-IEEE Computer
TL;DR: A new design paradigm reuses design-for-testability and debug resources to eliminate transient errors caused by terrestrial radiation in chip designs.
Abstract: Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.
01 Jan 2000
TL;DR: This chapter discusses mixed-Signal testing, which involves both direct and indirect testing of analog and mixed-signal circuits, and the challenges and benefits of using either the DSP or DAC method.
Abstract: CHAPTER 1: OVERVIEW OF MIXED-SIGNAL TESTING 1.1 Mixed-Signal Ciruits 1.2 Why Test Mixed-Signal Devices 1.3 Post-Silicon Production Flow 1.4 Test and Diagnostic Equipment 1.5 New Product Development 1.6 Mixed-Signal Testing Challenges CHAPTER 2: THE TEST SPECIFICATION PROCESS 2.1 Device Data Sheets 2.2 Generating the Test Plan 2.3 Components of a Test Program 2.4 Summary CHAPTER 3: DC AND PARAMETRIC MEASUREMENTS 3.1 Continuity 3.2 Leakage Currents 3.3 Power Supply Currents 3.4 DC References and Regulators 3.5 Impedance Measurements 3.6 DC Offset Measurements 3.7 DC Gain Measurements 3.8 DC Power Supply Rejection Ratio 3.9 DC Common Mode Rejection Ratio 3.10 Comparator DC Tests 3.11 Voltage Search Techniques 3.12 DC Tests for Digital Circuits 3.13 Summary CHAPTER 4: MEASUREMENT ACCURACY 4.1 Terminology 4.2 Calibrations and Checkers 4.3 Dealing with Measurement Error 4.4 Basic Data Analysis 4.5 Summary CHAPTER 5: TESTER HARDWARE 5.1 Mixed-Signal Tester Overview 5.2 DC Resources 5.3 Digital Subsystem 5.4 AC Source and Measurement 5.5 Time Measurement System 5.6 Computing Hardware 5.7 Summary CHAPTER 6: SAMPLING THEORY 6.1 Analog Measurements Using DSP 6.2 Sampling and Reconstruction 6.3 Repetitive Sample Sets 6.4 Synchronization of Sampling Systems 6.5 Summary CHAPTER 7: DSP-BASED TESTING 7.1 Advantages of DSP-Based Testing 7.2 Digital Signal Processing 7.3 Discrete-Time Transforms 7.4 The Inverse FFT 7.5 Summary CHAPTER 8: ANALOG CHANNEL TESTING 8.1 Overview 8.2 Gain and Level Tests 8.3 Phase Tests 8.4 Distortion Tests 8.5 Signal Rejection Tests 8.6 Noise Tests 8.7 Simulation of Analog Channel Tests 8.8 Summary CHAPTER 9: SAMPLED CHANNEL TESTING 9.1 Overview 9.2 Sampling Considerations 9.3 Encoding and Decoding 9.4 Sampled Channel Tests 9.5 Summary CHAPTER 10: FOCUSED CALIBRATIONS 10.1 Overview 10.2 DC Calibrations 10.3 AC Amplitude Calibrations 10.4 Other AC Calibrations 10.5 Error Cancellation Techniques 10.6 Summary CHAPTER 11: DAC TESTING 11.1 Basics of Converter Testing 11.2 Basic DC Tests 11.3 Transfer Curve Tests 11.4 Dynamic DAC Tests 11.5 DAC Architectures 11.6 Summary CHAPTER 12: ADC TESTING 12.1 ADC Testing Versus DAC Testing 12.2 ADC Code Edge Measurements 12.3 DC Tests and Transfer Curve Tests 12.4 Dynamic ADC Tests 12.5 ADC Architectures 12.6 Tests for Common ADC Applications 12.7 Summary CHAPTER 13: DIB DESIGN 13.1 DIB Basics 13.2 Printed Circuit Boards (PCBS) 13.3 DIB Traces, Shields, and Guards 13.4 Transmission Lines 13.5 Grounding and Power Distribution 13.6 DIB Components 13.7 Common DIB Circuits 13.8 Common DIB Mistakes 13.9 Summary CHAPTER 14: DESIGN FOR TEST (DFT) 14.1 Overview 14.2 Advantages of DfT 14.3 Digital Scan 14.4 Digital BIST 14.5 Digital DfT for Mixed-Signal Circuits 14.6 Mixed-Signal Boundary Scan and BIST 14.7 Ad Hoc Mixed-Signal DfT 14.8 Subtle Forms of Analog DFT 14.9 IDDQ 14.10 Summary CHAPTER 15: DATA ANALYSIS 15.1 Introduction to Data Analysis 15.2 Data Visualization Tools 15.3 Statistical Analysis 15.4 Statistical Process Control (SPC) 15.5 Summary CHAPTER 16: TEST ECONOMICS 16.1 Profitability Factors 16.2 Direct Testing Costs 16.3 Debugging Skills 16.4 Emerging Trends 16.5 Summary
TL;DR: SOCRATES as discussed by the authors is an automatic test pattern generation system for combinational and scan-based circuits based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures.
Abstract: An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >
18 Oct 1998
TL;DR: An overview of current industrial practices as well as academic research in core-based IC design is provided and the challenges for future research are described.
Abstract: Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overview of current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA and IEEE P1500 and describe the challenges for future research.
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