Topic
Design for testing
About: Design for testing is a research topic. Over the lifetime, 3946 publications have been published within this topic receiving 63049 citations. The topic is also known as: Design for Testability, DFT.
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Book•
07 Apr 2013
TL;DR: This book provides a careful selection of essential topics on all three types of circuits, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods.
Abstract: Today's electronic design and test engineers deal with several types of subsystems, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods. This book provides a careful selection of essential topics on all three types of circuits. The outcome of testing is product quality, which means "meeting the user's needs at a minimum cost". The book includes test economics and techniques for determining the defect level of VLSI chips. Besides being a textbook for a course on testing, it is a complete testability guide for an engineer working on any kind of electronic device or system or a system-on-a-chip.
1,484 citations
TL;DR: A new design paradigm reuses design-for-testability and debug resources to eliminate transient errors caused by terrestrial radiation in chip designs.
Abstract: Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.
600 citations
TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Abstract: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.
529 citations
Book•
01 Jan 2000
TL;DR: This chapter discusses mixed-Signal testing, which involves both direct and indirect testing of analog and mixed-signal circuits, and the challenges and benefits of using either the DSP or DAC method.
Abstract: CHAPTER 1: OVERVIEW OF MIXED-SIGNAL TESTING 1.1 Mixed-Signal Ciruits 1.2 Why Test Mixed-Signal Devices 1.3 Post-Silicon Production Flow 1.4 Test and Diagnostic Equipment 1.5 New Product Development 1.6 Mixed-Signal Testing Challenges CHAPTER 2: THE TEST SPECIFICATION PROCESS 2.1 Device Data Sheets 2.2 Generating the Test Plan 2.3 Components of a Test Program 2.4 Summary CHAPTER 3: DC AND PARAMETRIC MEASUREMENTS 3.1 Continuity 3.2 Leakage Currents 3.3 Power Supply Currents 3.4 DC References and Regulators 3.5 Impedance Measurements 3.6 DC Offset Measurements 3.7 DC Gain Measurements 3.8 DC Power Supply Rejection Ratio 3.9 DC Common Mode Rejection Ratio 3.10 Comparator DC Tests 3.11 Voltage Search Techniques 3.12 DC Tests for Digital Circuits 3.13 Summary CHAPTER 4: MEASUREMENT ACCURACY 4.1 Terminology 4.2 Calibrations and Checkers 4.3 Dealing with Measurement Error 4.4 Basic Data Analysis 4.5 Summary CHAPTER 5: TESTER HARDWARE 5.1 Mixed-Signal Tester Overview 5.2 DC Resources 5.3 Digital Subsystem 5.4 AC Source and Measurement 5.5 Time Measurement System 5.6 Computing Hardware 5.7 Summary CHAPTER 6: SAMPLING THEORY 6.1 Analog Measurements Using DSP 6.2 Sampling and Reconstruction 6.3 Repetitive Sample Sets 6.4 Synchronization of Sampling Systems 6.5 Summary CHAPTER 7: DSP-BASED TESTING 7.1 Advantages of DSP-Based Testing 7.2 Digital Signal Processing 7.3 Discrete-Time Transforms 7.4 The Inverse FFT 7.5 Summary CHAPTER 8: ANALOG CHANNEL TESTING 8.1 Overview 8.2 Gain and Level Tests 8.3 Phase Tests 8.4 Distortion Tests 8.5 Signal Rejection Tests 8.6 Noise Tests 8.7 Simulation of Analog Channel Tests 8.8 Summary CHAPTER 9: SAMPLED CHANNEL TESTING 9.1 Overview 9.2 Sampling Considerations 9.3 Encoding and Decoding 9.4 Sampled Channel Tests 9.5 Summary CHAPTER 10: FOCUSED CALIBRATIONS 10.1 Overview 10.2 DC Calibrations 10.3 AC Amplitude Calibrations 10.4 Other AC Calibrations 10.5 Error Cancellation Techniques 10.6 Summary CHAPTER 11: DAC TESTING 11.1 Basics of Converter Testing 11.2 Basic DC Tests 11.3 Transfer Curve Tests 11.4 Dynamic DAC Tests 11.5 DAC Architectures 11.6 Summary CHAPTER 12: ADC TESTING 12.1 ADC Testing Versus DAC Testing 12.2 ADC Code Edge Measurements 12.3 DC Tests and Transfer Curve Tests 12.4 Dynamic ADC Tests 12.5 ADC Architectures 12.6 Tests for Common ADC Applications 12.7 Summary CHAPTER 13: DIB DESIGN 13.1 DIB Basics 13.2 Printed Circuit Boards (PCBS) 13.3 DIB Traces, Shields, and Guards 13.4 Transmission Lines 13.5 Grounding and Power Distribution 13.6 DIB Components 13.7 Common DIB Circuits 13.8 Common DIB Mistakes 13.9 Summary CHAPTER 14: DESIGN FOR TEST (DFT) 14.1 Overview 14.2 Advantages of DfT 14.3 Digital Scan 14.4 Digital BIST 14.5 Digital DfT for Mixed-Signal Circuits 14.6 Mixed-Signal Boundary Scan and BIST 14.7 Ad Hoc Mixed-Signal DfT 14.8 Subtle Forms of Analog DFT 14.9 IDDQ 14.10 Summary CHAPTER 15: DATA ANALYSIS 15.1 Introduction to Data Analysis 15.2 Data Visualization Tools 15.3 Statistical Analysis 15.4 Statistical Process Control (SPC) 15.5 Summary CHAPTER 16: TEST ECONOMICS 16.1 Profitability Factors 16.2 Direct Testing Costs 16.3 Debugging Skills 16.4 Emerging Trends 16.5 Summary
525 citations
Book•
01 Jul 2006
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
522 citations