Showing papers on "Design for testing published in 1977"

Test generation for large logic networks

Abstract: A system for automatic test pattern generation for large logic networks is described. The network to be tested is assumed to comply with a set of ground rules for testability. The system includes features for automatic subdivision of the network into easily tested sub-networks, automatic test generation programs, and a post-processor which produces a highly efficient test program. Applications to fault diagnosis, and to fast processing of design changes and variations for machine features are considered.

Automatic checking of logic design structures For compliance with testability ground rules

Abstract: Specification of a set of design ground rules greatly simplifies the problems of testing and test generation for complex logic structures. This paper describes a fast and effective method for testing compliance of logic network designs to testability ground rules. The technique used is similar to logic simulation and may be performed as part of the design verification process. Very large designs may be checked quickly. The system provides an effective early warning tool for the logic designer and test engineer.

Logal: a CHDL for Logic Design and Synthesis of Computers

Abstract: A computer hardware description language can be a practical and economical tool for driving a comprehensive automated design facility for a large-scale computer environment. The logic designer must optimize many conflicting requirements, including the following:

Feasibility demonstration of an automated design system

Abstract: M. N. Matelan recently developed an abstract model for the control system design process (Matelan, 1976). Several features of this CSD model make it an attractive structure for an automated design system. These features include a method of stating the design problem independant of any realization technology and an approach which divides the design problem into a series of contingencies to be tested, related tasks to be performed as necessary, and a monitor strategy which controls the time sequencing of these contingency/task pairs. The concept of hardware binding is also introduced, which facilitates the simultaneous development of hardware and software.