Showing papers on "Design for testing published in 1982"

Design for Testability—A Survey

Abstract: This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.

Boolean comparison of hardware and flowcharts

Abstract: Boolean comparison is a design verification technique in which two logic networks are compared for functional equivalence using analysis rather than simulation. Boolean comparison was used on the IBM 3081 project to establish that hardware flowcharts and the detailed hardware logic design were functionally equivalent. Hardware flowcharts are a graphic form of a hardware description language which describes the logical behavior of the machine in terms of the inputs, outputs, and latches. The logical correctness of the hardware flowcharts was previously established via cycle simulation. The concepts and techniques of Boolean comparison as used on the IBM 3081 project are described.

Design verification system for large-scale LSI designs

Abstract: This paper describes the changing environment of large-scale hardware designs as influenced by technology advancements and the growing use of design verification in the design implementation process. The design verification methodology presented here saved some 66% from the 3081 product schedule, when compared with a schedule utilizing a conventional verification method, on almost 800 000 LSI logic circuits. The paper discusses the use of software modeling techniques to verify LSI hardware designs, methods used for deciding when modeling should be stopped and hardware can be built with sufficient assurance to permit additional verification to continue on the hardware, methods for testing the hardware as it is assembled into a very large processor complex, and the organization of the design verification system to avoid duplicate creation of test cases for different stages of the design process. Experiences encountered in designing and verifying the 3081 system, a discussion of some shortcomings, and an endorsement of certain techniques and improvements for use in future designs are also presented.

Fault Diagnosis of MOS Combinational Networks

Abstract: The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks.

Design for Testability

Abstract: This presentation will discuss the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs. These techniques include the three main areas of Design for Testability, 1) Ad Hoc approaches; 2) Structured approaches; and, 3) Self Test/Built-in Test approaches.

In-situ testability design (ISTD)—A new approach for testing high-speed LSI/VLSI logic

Abstract: After a discussion of the main problems encountered in conventional methods used for testing high-speed LSI/VLSI logic, a new approach, to be called the "in-situ testability design" (ISTD), will be presented. The approach consists of extending the use of latches and serial-shift arrangements (SSA's) provided in the hardware system to be tested, by incorporating on-chip feedback arrangements designed in such a way that the chips and modules will be self-sufficient for testability-that they will be testable in-situ and in-isolation, despite their interconnections after being assembled in the system. By proper design, chips can be made testable also on-wafer prior to their dicing. For economical implementation, arrangements for sharing the use of latches and multiplexors will be introduced and explained. The ISTD approach will fundamentally simplify and facilitate the testing of high-speed LSI/VLSI logic and greatly reduce the costs of test equipment and testing. Design procedure for its implementation, and test strategy based on its use, will be described.

The impact of testing on VLSI design methods

Abstract: The question `why design for testability'? is answered by discussing some existing test philosophies. Exhaustive testing, functional testing, and structural testing are treated, also with regard to their usefulness for VLSI circuits. There is no general agreement on how to design for testability. Various approaches exist, and each has its specific applications. Some of these approaches are discussed in detail, also regarding the influence of the complexity on necessary CAD tools for test pattern generation.

Hardware logic design faults-a classification and some measurements

Abstract: The authors analyse the types and quantities of logic hardware design faults found and corrected during development commissioning, system validation, production introduction and field support for an MSI implementation of a medium range computer system. It is found that the faults can be classified into fault types which, with particular exceptions, apply generally to all units of the mainframe design. The results show that approximately 20percent of the faults found were attributable to specification problems, 30percent to the environment and 50percent to realisation. The implications of this information with respect to the design of VLSI systems is discussed. 5 references.

Automated Conversion of Design Data for Building the IBM 3081

Abstract: The Manufacturing Release Processing System for handling the dual design methodology employed by IBM in the design of the 3081 is described in this paper. This methodology consists of (Part 1) the design of basic building blocks, such as standard circuits and structured gate arrays, on which these standard circuits can be placed and interconnected during (Part 2), when numerous unique devices are designed to perform the various logical functions within the processor. This dual design methodology created some difficult challenges to IBM's CAD/CAM system designers. This paper focuses on the automated release process and how it meets the specific challenges of processing large volumes of design data in the minimum time demanded by fast, controlled implementation of engineering changes.

An Enhancement of LSSD to Reduce Test Pattern Generation Effort and Increase Fault Coverage

Abstract: In this paper we propose designs of latches which can be used in Level Sensitive Scan Design (LSSD). These new designs can use the existing software support for design rule checks but result into a reduction of effort in test pattern generation and provide a better fault coverage. The system performance is not degraded with the use of latches proposed in this paper.

An Interactive Testability Analysis Program - ITTAP

Abstract: ITTAP is a testability analysis program developed at the ITT-LSI technology center. In this paper we describe a testability measure for the test length and discuss the use of the selective trace concept for testability calculations. It is shown that ITTAP provides an order of magnitude improvement in run time over existing programs like SCOAP.

Operational Aspects of Design Automation for the IBM 3081

Abstract: The processes for design and release of LSI chips, thermal conduction modules (TCMs), and boards on the IBM 3081 Processor are highly automated, using the Engineering Design System. This paper describes the automated and manual operations involved in the process of design and release of the various packaging levels to Manufacturing for fabrication and test. The Engineering Design System (EDS) includes a data base of programs and rules for the operations involved in designing and documenting a product. The design system contains all rules, definitions, and programming requirements for system design and complete data transfer to Manufacturing and testing.

Advanced Methods for Testing VLSI Components

Abstract: All methods for testing VLSI components are based on design for testability. Since VLSI complexity necessitates the utilization of regular design structures the emphasis of this paper is on how to exploit regularity in order to obtain easily testable components. Besides memories which are not considered here, the most important regular structures are programmable logic arrays (PLAs). Great effort has been spent on designing testable PLAs. The tendency is now towards universal test sets and self-test. Of equal importance are bit-sliced architectures. Applying the well-founded theory of iterative logic arrays (ILAs) to bit slices has produced very promising results. Self-test is entering this area, too. An example of a 32-bit execution unit combining bit-sliced architecture and self-test concludes this paper.