Showing papers on "Design for testing published in 1983"

Design for testability—A survey

Abstract: This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.

A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays

Abstract: In this paper, the validity of single fault assumption in deriving diagnostic test sets is examined with respect to crosspoint faults in programmable logic arrays (PLA's). The control input procedure developed here can be used to convert PLA's having undetectable crosspoint faults to crosspoint-irredundant PLA's for testing purposes. All crosspoints will be testable in crosspoint-irredundant PLA's. The control inputs are used as extra variables during testing. They are maintained at logic 1 during normal operation. A useful heuristic for obtaining a near-minimal number of control inputs is suggested. Expressions for calculating bounds on the number of control inputs have also been obtained.

Design for Test Calculus: An Algorithm for DFT Rules Checking

Abstract: A new one-pass algorithm for checking networks for compliance to a set of Design for Test (DFT) rules is presented. The algorithm is based on a "Design For Test Calculus" which defines various types of signals and nodes in the network, signal sets attached to node's inputs and outputs, and rules for transferring signal sets through nodes. The rule checking is accomplished by examining the characteristic contents of the signal sets transferred. The calculus is capable of handling a wide variety of "test point flip-flops" and test access schemes, and has features that make hierarchical rule checking feasible.

Semi-custom IC design and VLSI

Abstract: * Chapter 1: Introduction * Chapter 2: Introduction to silicon fabrication * Chapter 3: Review of bipolar and MOS technologies * Chapter 4: Structure of semi-custom integrated circuits * Chapter 5: Selection of semi-custom techniques, supplier and design route * Chapter 6: Circuit design techniques * Chapter 7: Logic design with emphasis on ASM method * Chapter 8: The programmable logic array: implementation and methodology * Chapter 9: PLA and ROM based design * Chapter 10: CAD and design automation * Chapter 11: A review of simulation techniques * Chapter 12: Partitioning, placement and automated layout * Chapter 13: Design for testability * Chapter 14: Silicon compilers and VLSI * Chapter 15: Practical aspects of semi-custom design

Design for testability.

Abstract: Testing of circuits with a few hundred logic functions can, in general be performed by the use of selected logic stimuli (Mueldorf and Savkav (1)). Exhaustive testing of circuits demands that all possible logic states in which a circuit can exist must be considered. Automatic test pattern generation (ATPG) methods (Williams and Parker (2), Papaionnou (3), Schnurmann et al (4)) can be used to effect in determining the test stimuli (or test vectors) required to achieve or approximate such an exhaustive test. For combinational circuits where the present states of the output variables are a function only of the present states of the input variables, exhaustive testing requires derivation of a test sequence to create all of the possible input combinations and check the outputs for correct responses. These input stimuli can be applied from automatic test equipment systems (ATE) and the responses can subsequently be sensed by the same equipment.

Automating Technology Relative Logic Synthesis and Module Selection

Abstract: This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the design process.

Design Work-Stations

Abstract: The requirements of a family of design work-stations for IC/CAD are presented and areas in which they will find major application are described.