Showing papers on "Design for testing published in 1984"
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TL;DR: Critical path tracing determines fault detection without explicit fault simulation, and appears to be a more efficient alternative to conventional methods.
Abstract: Critical path tracing determines fault detection without explicit. fault simulation. It appears to be a more efficient alternative to conventional methods.
254 citations
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TL;DR: The testability of two well-known array multiplier structures is studied in detail and it is shown that, with appropriate cell design, array multipliers can be designed to be very easily testable.
Abstract: Array multipliers are well suited for VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are difficult to test. This correspondence shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called C-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures is studied in detail. The conventional design of the carry–save array multiplier is modified. The modified design is shown to be C-testable and requires only 16 test patterns. Similar results are obtained for the Baugh–Wooley two's complement array multiplier. A modified design of the Baugh–Wooley array multiplier is shown to be C-testable and requires 55 test patterns. The C-testability of two other array multipliers, namely the carry–propagate and the TRW designs, is also presented.
117 citations
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01 Oct 1984
TL;DR: The paper presents a model for optimum partitioning of tasks over a multiple-processor system and the algorithmic approaches to the problem are briefly described.
Abstract: MODELS OF THE TASK ASSIGNMENT PROBLEM IN DISTRIBUTED SYSTEMS Mario Lucertini Dipartirnento di Informatica e Sistemistica dell'Universiti di Roma e Istituto di Analisi dei Sistemi ed Informatica del C.N.R., Viale Manzoni 30, 00185, Roma The paper presents a model for optimum partitioning of tasks over a multiple-processor system. The minimization of the interprocessor. communications overhead and/or the message average delay are considered as a design criterion. The algorithmic approaches to the problem are briefly described and improuvements to the case of multiple copies of tasks are considered. A large set of references covering the area are included.
81 citations
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TL;DR: A new design of universally testable PLA's is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA.
Abstract: A new design of universally testable PLA's is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA. The proposed design has the following properties. 1) It can be tested with function-independent test patterns; hence, no test pattern generation is required. 2) The amount of extra hardware is significantly decreased compared to the previous designs of universally testable PLA's. 3) Very high fault coverage is achieved, i. e., all single and multiple stuck faults, crosspoint faults, and adjacent line bridging faults are detected. 4) It is appropriate for built-in testing approaches. 5) It can be applied to the high-density PLA's using array folding techniques.
64 citations
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16 Oct 1984TL;DR: In this article, a technique for designing easily testable PLAs is presented, which consists of the addition of a small number of bit lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and devices tested.
Abstract: A new technique for designing easily testable PLAs is presented. The salient features of this technique are: 1) low overhead, 2) high fault coverage, 3) simple design, 4) little or no impact on normal operation of PLA and 5) elimination of the need for test pattern generation. This technique consists of the addition of a small number of bit lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and dev ices tested. Using this technique all multiple stuck-at faults, as well as all multiple extra and multiple missing device faults, are detected.
59 citations
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45 citations
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TL;DR: In this article, the authors present a testability and self-testing approach for bit-serial signal processors for an integrated circuit consisting of bit serial data paths whose integration level requires approximately 120,000 transistors packaged in a 68-pin chip carrier.
Abstract: This article presents design for testability and self-testing approaches for bit-serial signal processors?specifically, for an integrated circuit consisting of bit-serial data paths whose integration level requires approximately 120,000 transistors packaged in a 68-pin chip carrier. The bit-serial architecture lends itself to a scan-type approach for functional testing with minimum design modification. The functional verification testing requires less than one percent additional hardware, plus a minimum of four additional I/O package pins. Although less straightforward, self-testing was still accomplished without execessive penalties. A potential solution to the problem of data integrity of the interchip communication lines required only a minimum amount of hardware and additional I/O pins.
16 citations
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TL;DR: Two methods aimed at achieving total coverage are presented: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation, and the other employs a test patterngeneration algorithm (the FAN algorithm) that enables us to generate a test patterns for any detectable fault within the allowed time limits.
Abstract: Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.
14 citations
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16 Oct 1984
TL;DR: A strategy to locate failures at a functional level is presented and illustred on an actual faulty circuit.
Abstract: The GAPT project (automatic generation of test programs for microprocessors) is in its final phase. The various components of the project (method, software tools and hardware environment) are presented. A strategy to locate failures at a functional level is presented and illustred on an actual faulty circuit.
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16 Oct 1984
TL;DR: A comprehensive analysis of the cost effectiveness of using Mixed-Mode Self-Test (MMST) in VLSI based designs and the test results of experimenting with some Sperry designs are reported.
Abstract: This paper presents a comprehensive analysis of the cost effectiveness of using Mixed-Mode Self-Test (MMST) in VLSI based designs. The justification and impact of using MMST on the products life cycle (semiconductor, factory, & field) at all levels of integration (wafer, PCB, & unit) are discussed. Different implementations of the MMST technique are presented. This includes the hardware details of the self-test circuitry and the formalized test procedures for every MMST technique. The design for test rules for handling buried sequential logic, like RAMs and registers. and bi-directional buses are also discussed. The test results of experimenting with some Sperry designs are reported. Finally, the impact of MMST on the chip area and the physical deign issues of the self-test circuitry are analyzed, and the overall conclusions of our work are documented.
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01 Oct 1984
TL;DR: This study provides the foundation for a logical and cost-effective program for applying Artificial Intelligence to electronic testability for the military.
Abstract: : This study provides the foundation for a logical and cost-effective program for applying Artificial Intelligence to electronic testability for the military. Emphasis is on those artificial intelligence (AI) techniques capable of practical application with low risk development within three to five years. The primary near term applications are design support and maintenance applications. Eight potential applications are developed and evaluated: 1) Computer Aided Preliminary Design for Testability, 2) Smart Built-in Test, 3) Smart System Integrated Test, 4) Box Level Maintenance Expert, 5) System Level Maintenance Expert, 6) Smart Maintenance Expert, 7) Automatic Test Program Generation, and 8) Smart Bench Tester. All of these application opportunities can be implemented with engineering workstations which are becoming available directly to designers. Originator-supplied keywords include: Artificial intelligence; Automated diagnostics; BIT; Design for testability; Fault isolation; Predictive maintenance; Engineering workstations.
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NEC1
TL;DR: Logic verification using automated test generation and simulation is described, in which functional design and structural design results are compared for functional equivalence.
Abstract: Logic verification using automated test generation and simulation is described, in which functional design and structural design results are compared for functional equivalence. This new approach has been developed as a function of a mixed level simulator, MIXS1, and has strengthened MIXS top-down and bottom-up design support capabilities.
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25 Jun 1984TL;DR: The major components of IDAS include: heuristic controllability/observability (C/O) analysis, prediction of testing costs, tools for evaluation, display and improvement of testability, and C/O guided automatic test pattern generator.
Abstract: A general overview on an Integrated Design for Testability and Automatic Test Pattern Generation System (IDAS) is given. The major components of IDAS include: heuristic controllability/observability (C/O) analysis, prediction of testing costs, tools for evaluation, display and improvement of testability, and C/O guided automatic test pattern generator. The IDAS system includes also the logic and concurrent fault simulator CADAT. A brief description of major components with a scenario how to use IDAS is given. Future research activities are discussed.
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16 Oct 1984TL;DR: A design for testability (DFT) structure for sequential machines requires augmentation of sequential machines by addition of an extra input and some associated logic and is suitable for built-in self-test (BIST).
Abstract: A design for testability (DFT) structure for sequential machines is presented. This design has the following characteristics: it requires augmentation of sequential machines by addition of an extra input and some associated logic; the test sequence is the same for all machines with a given number of input combinations, states, and outputs; it uses signature analysis to compact the output response; fault diagnosis is possible by obtaining intermediate signatures; and it is suitable for built-in self-test (BIST).
A systematic procedure for testing the sequential machines designed by this method is presented. The test length is also calculated. An example of a practical machine is used to illustrate the proposed scheme.
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24 Jan 1984
TL;DR: The potential role of computer aided testability in the design process is described, and five recommended testability tool categories discussed: Testability Allocation, Test Point Location, Testability Analysis, BIT Selector, and Automatic Test Program Generation.
Abstract: Much has been written on the poor testability of military electronics especially 'cannot duplicate' and 'retest OK' problems at organizational and depot level facilities, respectively. The resulting in creased logistics costs add significantly to system's overall life cycle costs. To be effective and reduce these costs, testability must be an integrated system development task where it is designed-in rather than added-to a product. A primary road-block to this approach has been a lack of widespread knowledge of testability design approaches and availability of tools to help the designer. As important as knowledge and availability are, a third facet is of at least equal importance, ease and efficiency of use. One means through which this last element can be fostered is through the development of computer aided testabil ity design tools. Practical Computer Aided Testability (CAT) design tools must integrate smoothly with both the traditional top-down design process (conceptual design, system design, subsystem design, detailed design) and other existing Computer Aided Design (CAD) tools. This paper discusses CAD systems and the level of their present support to testability. In particular, the potential role of computer aided testability in the design process is described, and five recommended testability tool categories discussed: Testability Allocation, Test Point Location, Testability Analysis, BIT Selector, and Automatic Test Program Generation. The role of these tools and their use during the design process along with their present state of development is described, as is the potential impact of integrating them with existing CAD systems.
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24 Jan 1984
TL;DR: The basic microprocessor BIT tests are defined including methods of modifying these tests to a specific microprocessor and the test hardware and software, which supports these tests, are described along with an example of its implementation.
Abstract: This paper provides the BIT (Built-In-Test) designer with a generalized test strategy for testing microprocessors (Mp). The basic microprocessor BIT tests are defined including methods of modifying these tests to a specific microprocessor. The test hardware and software, which supports the individual tests, are described along with an example of its implementation. Some design options and tradeoffs are made available to allow flexibility for diversified application. An example of this strategy using INTEL's 8086 microprocessor is provided.
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24 Jan 1984TL;DR: In this article, the authors describe a systematic, formalized and timely approach to designing avionics for testability at all maintenance levels, which will reduce many of the current problems in the field such as "RETEST OKs" and "CANNOT DUPLICATEs."
Abstract: The purpose of this paper is to describe a systematic, formalized and timely approach to designing avionics for Testability at all maintenance levels, which will reduce many of the current problems in the field such as "RETEST OKs" and "CANNOT DUPLICATEs." The approach was developed to be used by avionics designers and is recommended for Program Office personnel who specify requirements for avionics design. It was developed to provide a high level of testability to meet specified standards and to maximize the compatibility of the avionics with its support equipment. The objective of this approach to testability in design is to maximize the availability of the avionics system and minimize repair time, spares, and logistics support requirements. Key features of this paper are the systematic approach to designing for all maintenance levels and an integrated maintenance concept which will allow compatible system support, even if separate contractors perform the support at different maintenance levels.
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16 Oct 1984TL;DR: A critical look at the role testability analysis has been playing in IC design and an insight into what role it should assume in the future is provided and it is believed that testabilityAnalysis will eventually replace fault simulations.
Abstract: This paper takes a critical look at the role testability analysis has been playing in IC design and provides an insight into what role it should assume in the future. Traditionally, testability analysis was used to derive information on how testable a circuit is early enough in the design cycle so that the design could be modified to improve its testability before running either the fault simulation or the actual testgeneration programs. This approach would avoid wasting precious computer resources in using those two programs. More recently, two rather important applications have also been identified. The first is to use testability-analysis results as heuristics to guide the test-generation process in search of a solution (test vector). Testability-analysis programs have also been used to derive information normally provided by fault simulation. Due to these developments and the potential usefulness of the information it can provide, testability analysis is gaining more importance in the design cycle of integrated circuits.
Based upon our recent experiences in developing testability analysis and test-generation programs, we believe that testability analysis will eventually replace fault simulations. However, it is imperative that the burden not be shifted to the test-generation or testing processes. Instead, the ultimate role of testability analysis is to provide vital information for generating tests directly. It would provide at least an approximate solution to a very complex (NP-complete) problem through algorithms of less complexity. This approach promises a final solution to the challenge of VLSI test generation.
01 Jan 1984
TL;DR: The main objective of this research was to introduce an intelligent automatic Sequential Circuit Test System, SCIRTSS, driven by A Hardware Programming Language, AHPL, which can handle the test vector generation process for VLSI circuits in an early state of the design loop, even before the generation of the final technology dependent network logic list.
Abstract: The era of VLSI design necessitates the development of advanced Computer Aided Design tools. The main objective of this research was to introduce an intelligent automatic Sequential Circuit Test System, SCIRTSS, driven by A Hardware Programming Language, AHPL. SCIRTSS can handle the test vector generation process for VLSI circuits in an early state of the design loop, even before the generation of the final technology dependent network logic list.
The driving force of the test generation process is the intelligent search program. The search program, supported by a set of heuristics and an accurate function level simulator, generates the test sequence to propagate the single fault effect to a primary output of the circuit. The test sequence generated is a concatenation of the sequences generated by the repeated searches on the state-space of the design. These sequences are verified by a parallel fault simulator.
Design for testability techniques could be used to improve the test sequence generated. This system is user friendly and protable. Several circuits were tested under SCIRTSS, the results of some of them were introduced in this paper.
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16 Oct 1984
TL;DR: PALs (R), logic arrays, and gate arrays mounted on circuit boards present unique testing problems for the in-circuit tester such as oscillations when back-driving, initialization problems, and increased test development time.
Abstract: PALs (R), logic arrays, and gate arrays mounted on circuit boards present unique testing problems for the in-circuit tester such as oscillations when back-driving, initialization problems, and increased test development time. Some techniques to alleviate these problems are presented, including design for testability, suggestions for test programming, and features to look for in a test system.