Showing papers on "Design for testing published in 1986"

Macro Testing: Unifying IC And Board Test

Abstract: Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexity in both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couples both types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustom VLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term ?macro testing.? The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macros and the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro tests into a chip test.

VHDL - The Language

Abstract: The VHSIC hardware description language (or VHDL) provides a standard textual means of description for hardware components at abstraction levels ranging from the logic gate level to the digital system level It provides precise syntax and semantics for these hardware components, enabling design transfer both within and among organizations The language is designed to be efficiently simulated and natural for hardware designers In addition, it allows designers to represent information outside the primary range of language coverage, although the initial toolset does not support simulation at those levels (switch level, for example) Finally, by not restricting designers to a particular hardware technology or design style, the language permits wide industrial usage

Test Schedules for VLSI Circuits Having Built-In Test Hardware

Abstract: In this correspondence, the concept of a test schema which describes how a test methodology is to execute is introduced. We also introduce the powerful concept of an I path which is used to transfer data unchanged from one place in a circuit to another. The process of embedding a test schema into an actual circuit is described. This produces a test plan for the circuit which specifies the sequence of actions that need to be carried out to execute the test. A theory of test plan execution overlap is presented, and is used as the basis for constructing test schedules with optimal execution times.

Lower Overhead Design for Testability of Programmable Logic Arrays

Abstract: A new technique for designing easily testable PLA's is presented. The salient features of this technique are: 1) low overhead, 2) high fault coverage, 3) simple design, and 4) little or no impact on normal operation of PLA's. This technique consists of the addition of input lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and device can be tested. Using this technique, all multiple stuck-at faults, as well as all multiple extra and multiple missing device faults, are detected.

An Automatic DFT System for the Silc Silicon Compiler

Abstract: This article discusses design for testability automation for the Silc silicon compiler under development at GTE Laboratories, Inc. Our modular design for testability uses both built-in self-test and scan-path techniques for Slic's full custom VLSI designs. A test controller coordinates the testing of the chip's modules. Testability evaluation is performed using controllability/observability methods, and using a method based on information theory. A testable-by-construction approach is followed in order to synthesize blocks of testable logic. A testability ?expert? manages testability knowledge during the synthesis process and makes the ultimate testability decisions.

Design-for-Testability of PLA'S Using Statistical Cooling

Abstract: A method for designing easily testable PLA's with low overhead is presented. The method is based on a reduction of product lines and the addition of a small number of inputs. The required additional hardware is calculated using a statistical cooling algorithm. The presented design-for-testability method guarantees a 100 percent fault coverage with respect to multiple stuck-at faults and multiple missing/extra crosspoint faults.

Hardware Design Languages for Computer Design and Test

Abstract: A standard design and description language will result in a very rich tool base, increased ability to communicate design data, and improved productivity.

Testability: Barriers to Acceptance

Abstract: Design for testability sounds wonderful in theory, but if it is not used, or worse used to disadvantage, what good is it? With today's escalating technology and management's fear of commitment to a costly testing program, DFT practices are suffering. the author discusses the prominent barriers to accepting design for test: the impact of more advanced technology, the misunderstood role of testing, the lack of management's global view of sthe testing process, and the lack of integrasted tools. Testability standards are briefly discussed as a possible way to overcome these barriers.

A New Economical Implementation for Scannable Flip-Flops in MOS

Abstract: A New implementation for scannable flip-flops in MOS is economical for use in systems that use single latch design. The ?System Latch-Scannable Flop? (SL-SF) requires two additional transfer gates, two test clocks, and possibly a test mode signal. Hardware pernalties paid in SL-SF can be the least among other implementations with equivalent test functionality. This article discusses SL-SF only in the context of its scan-path implementation; its applicability to linear feedback shift-register-based self-test should be obvious.

Development of an automated storage and retrieval system for manufacturing assembly lines

Abstract: This paper describes the development considerations and logic of an automated storage and retrieval system (AS/RS). The system is used as a material handling system for a class of manufacturing assembly lines. First defined is the manufacturing environment from which the design objective and constraints are derived. Queueing and simulation models are employed to identify the key performance parameters, to evaluate design alternatives, and to compare different dispatching rules. Both hardware and software design concept and parameters are briefly reviewed. A work-in-process management policy and a line design concept associated with AS/RS are introduced.

Trends in Design for Testability

Abstract: This paper will present the currently used techniques in the area of Design for Testability. It will begin with the Ad Hoc approaches of In-Circuit techniques, Functional Testing and Signature Analysis. Then the Structured Approaches of Scan Design will be discussed. Finally the techniques of Self-Testing will be discussed such as BILBO, and Exhaustive Testing. With each of these areas, the trends in usage will be indicated.

Structured Design for Testability in Semicustom VLSI

Abstract: W ithin a very few years, integrated circuit technology has moved from large-scale integrated circuits to very large scale integrated circuits. The implementation of VLSI circuit technology has resulted in an increase in circuit density leading to logic gate counts three to five times greater than previously attained. As this change was taking place, it was noticed that the functions of VLSI chips were inherently more specialized than those of the earlier LSI parts. As the shift to VLSI continued, the degree of specialization of function began to be somewhat of a problem. With a few notable exceptions, logic systems that had tens of thousands of gates were so specialized that they could never be manufactured and sold in the quantities needed to make their manufacture economically feasible. I The development of the general-purpose LSI component known as the microprocessor did much to solve the problem of sufficient volume temporarily. Unfortunately, however, the microprocessor was unable to be the answer to all digital design problems. It was too slow in some cases and too complex in others; therefore, a costly full-custom design was often the only answer. Several ways of dealing with the cost and time involved in custom design have been developed. As custom VLSI circuits grew more complex, hierarchical and modular design techniques were applied to the custom design process so that some level of control could be maintained. These techniques tended to isolate the designer from some of the complexity of low-level circuit design, and they led to the development of the semicustom integrated circuit design methodology. With this methodology, a digital designer with a limited knowledge of IC design and fabrication could use previously designed macros, or modules, to develop complex integrated circuits. Methodologies have also been developed that call for several designs, each from a different designer, to be fabricated on a single wafer as a way of cutting the cost of prototype implementation. A significant problem that has remained and tended to worsen as IC technology has advanced is that of determining, in a cost-effective manner, whether or not a component has been manufactured correctly. It has been shown that the cost of testing a chip tends to increase as the square of the number of devices on the chip increases. 2 For some manufacturers, the cost of adequately testing chips with high circuit densities has become so high that they have accepted the risk of shipping defective parts. As circuit complexity has increased, concern has arisen that the limit to the attainable functional density of a chip will not be any physical parameter but instead will be the point at which it becomes untestable-that is, the point at which the chip, in production quantities, can no longer be costeffectively verified to be fault-free. This concern over testability translates into concern over the cost of doing business. A standard among people who are familiar with testing illustrates the problem: If it costs 30 to 50 cents to

Saturn: an automatic test generation system for digital circuits

Abstract: This paper describes a novel test generation system, called Saturn, for testing digital circuits. The system differs from existing test generation systems in that it allows a designer to specify the structure and behavior of a design at a collection of abstraction levels that mirror the design refinement process. The system exploits the abstract design formulations to increase the efficiency of test generation by ignoring irrelevant detail whenever possible. These capabilities are made possible by using general representation and reasoning methods based on logic, which provide a declarative representation of a design, and permit using a single inference procedure for reasoning both forwards and backwards through the design for test generation.

Scheme for achieving continuously variable delay in digital test equipment

Abstract: A design for test equipment which introduces a controlled variable delay into digitally encoded transmission links without loss of data is described

Testability measures on a state-of-the-art circuit

Abstract: : By means of design for testability (DFT) techniques, the NOSC Test Technology Office (Code 936) evaluated testability improvements in a state-of-the-art printed-circuit board. Data were gathered to provide a direct comparison among various testability figure of merit (TFOM) tools. Keywords include: Design for testability (DFT); Printed-circuit boards; MIL-STD 2165; STAMP; and LOGMOD.

Mathematical Systems Theory and Design Automation

Abstract: This paper discusses some aspects for the application of systems theory in CAD workstations for computer design. The main concern is to consider multi-strata systems specifications as a useful framework to model the design process.In addition systems theory is considered to provide fundamental means for the construction of optimal specifications at the different levels. Furthermore it provides the right source for the selection of proper mappings to relate the different levels to each other.As an example the introduced concepts are demonstrated by a 4-strata systems specification 4-STRAT-SPEC-S which uses finite state machines.As a research-goal,the paper discusses some of the motivations for the use of finite state machine theory to enhance current existing design stations to improve “Design For Testability” features.