Showing papers on "Design for testing published in 1987"

HSS--A High-Speed Simulator

Abstract: The High-Speed Simulator (HSS) is a fast and flexible system for gate-level fault simulation Originally limited to combinational logic, it is being extended to handle sequential logic It may also prove useful as a functional simulator The speed of HSS is obtained by converting the cycle-free portions of a circuit into optimized machine code for a general-purpose computer This compiled code simulates the circuit's response for 16 or 32 test patterns in parallel Faults are injected into the circuit by changing the machine instruction corresponding to the fault location From the range of speeds seen in recent measurements, we take 240 million gates per second as a fair general estimate of the speed of 2-valued simulation running on a 3081/K computer For 3-valued simulation, divide by 29 The paper discusses the merits and drawbacks of the HSS strategy It also sketches the extensions of HSS to model sequential logic and the various applications of HSS These include functional verification, design for testability, good machine signatures, and accurate simulation of transistor-level defects in certain CMOS technologies Finally, there is some discussion of how the simulation requirements of future designs can be met, and of the lessons to be drawn from long-term experimentation with HSS

Designing CMOS Circuits for Switch-Level Testability

Abstract: Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.

Optimal Layout to Avoid CMOS Stuck-Open Faults

Abstract: A set of layout rules is presented to cope with CMOS stuck-open faults by a design for testability at the layout-level. In applying these rules, open connections may either be avoided or their effects can be described by an easily detectable type of open faults known from CMOS inverters and NMOS logic. Hence, remaining open faults are usually covered by a complete stuck-at test pattern set.

Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories

Abstract: This paper presents a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for CAMs and RAMs are developed for a broad class of pattern sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design for testability strategy allows an entire w word CAM to be read in just one operation with a resulting speed up in testing as high as w. In the case of an n bit RAM, the improvement in test efficiency is by a factor of O(√n). The overall reduction in testing time is considerable for large size memories.

The IBM VHDL Design System

Abstract: This paper presents the IBM VHDL Design System. This set of Computer Aided Engineering (CAE) design tools, built around the VHSIC Hardware Description Language (VHDL) and developed for IBM internal use, along with other design automation tools, is used by IBM design engineers to develop computer hardware. The function and operation of each piece of the system is described. IBM usage and some of the problems encountered are also discussed.

Testing Programmable Logic Arrays by Sum of Syndromes

Abstract: Syndrome testing is a simple and effective fault detection technique applicable to many general circuits. It is particularly useful in two-level circuits, such as programmable logic arrays (PLA's). For a multiple-output network, like PLA's, existing methods test the individual syndromes for each function, where a fault should be detectable in at least one output. This paper shows that the weighted sum of syndromes of all the outputs covers all single stuck-at-faults, bridging faults, and cross-point faults. Primary input faults are also covered except in one special case which requires some preventive design for testability. This results in the use of one test to cover all single faults.

Scan path testing of a multichip computer

Abstract: On-chip test support circuitry has been developed for a 32b multichip VLSI computer. The test support consists of a test PLA and a 45MHz diagnostic interface port that multiplexes up to 16 serial scan paths. While requiring less than 10% of chip area and power, it supports testing, characterization and diagnosis from chip to system level.

Report: Computer-aided engineering and design for interconnection technology

Abstract: The vertical integration of the design and manufacturing elements of AT&T provides the right environment for developing and using an end-to-end computer-aided design process. We have applied this process to the design of the complete hierarchy of interconnection levels1 — the integrated circuit (IC) package, circuit pack, backplane, multibackplane unit, frame, and system. Computer aids are available for the initial design phases (computer-aided engineering, or CAE) and the follow-on, detailed design phases and interfaces to manufacturing (computer-aided design, including computer-aided test design, or CAD.) The computer-aided design process has been in use throughout the AT&T R&D community for many years,2 and it is steadily enhanced to increase its benefits.

New methods for the compaction testing of multiple-output digital circuits

Abstract: A new approach, called "space compaction", is proposed for the testing of multiple-output circuits. Testing is applied in parallel to all outputs and produces a single signature, that is an attribute or set of attributes which change in the presence of a fault. Space compaction testing is directly applicable to built-in self-test. We prove that criteria exist for detecting whether or not a line is testable, using a deterministic approach without the need for extensive simulation. Further, the fault model is extended to include bridging faults, rather than being limited solely to single stuck-at faults. General conditions are presented which specify deterministically when a fault is testable by a spectral sum signature. Such a signature is composed of a weighted sum of one or more spectral coefficients, which simply reflect a form of counting compaction applied to all outputs. The syndrome count is a special case. From the evaluation of the conditions, guidelines for design for testability are inferred. Of great significance is the application of the theory to highly structured multiple-output networks like programmable logic arrays (PLA's). These occur frequently in current VLSI designs, and they can be deeply embedded within circuits, so that they are hard to test. For these examples space compaction testing gives full coverage for all single stuck-at faults, bridging faults, and cross-point faults.

Design for testability-the need for change

Abstract: There are at present very few higher educational establishments that are approaching the teaching of electronics design for testability in any realistic way. However, Brunel University has made efforts to include test topics in undergraduate, postgraduate and industrial courses, and for the future has plans to establish an Institute of Test Engineering.

Techniques and issues in testing and validation of VLSI systems

Abstract: Publisher Summary This chapter presents the techniques and tools that help to solve the very large scale integrated (VLSI) design validation and testing crisis of the 1980s. It introduces the fabrication of integrated circuits and sources of failure. It provides brief overview of the metal-oxide semiconductor-integrated circuit (MOS-IC) fabrication technology and discusses process monitoring. The implementation of an IC chip involves three major steps: design, mask making, and fabrication. The chapter discusses three different kinds of design validation tools: simulation tools, performance verification tools, and logic verification tools. It classifies the major techniques for achieving reliable operation into fault avoidance, fault detection, masking redundancy, and dynamic redundancy categories. Special emphasis is given on test pattern generation for off-line testing. The basics of off-line testing are introduced. The chapter explains different test generation techniques and describes exhaustive, random, algebraic, structural, functional, and architectural approaches to test generation. It describes design for testability techniques and discusses built-in self-test.

Testability - getting the message across to the 'mature' engineer

Abstract: The new graduate intake into the electronics industry tends to have had little or no formal teaching in design for testability. This article suggests ways of getting across the DFT message to both newly graduated and practising engineers.

VLSI Testing: DFT Strategies and CAD Tools

Abstract: The increasing complexity of the design primitives used and the higher degree of integration now possible are two factors that impede testability. This is due to the higher number of gates which is not matched by an adequate increase in pin count. Using CAD tools, the cost of designing such “more complicated chips” can of course be kept within reasonable limits, but the cost of test preparation will explode due to the level of complexity. Another fact is that semicustom design is on the increase. Bearing in mind that the intention underlying semicustom design is to achieve low-volume production of a great variety of circuits in a very short turn-around time, it is obvious that the factors of high cost and long test preparation time are becoming more critical, as compared with universal chips produced in large quantities. Thus it is essential to automate test preparation by using adequate CAD tools, such as automatic test pattern generation (ATPG). The basis for the effectiveness of these tools is a strict design for testability (DFT), even if the chip area becomes somewhat larger.

The Design of Dedicated 32-Bit Processors

Abstract: NTT has developed two CMOS 32-bit processor VLSI families dedicated to communication systems: DIPS is for on-line information processing, while DEX is for an electronic switching system. The design methodology uses a hierarchical design technique, a common design language and database, and automated layout based on a standard cell approach. Gate density was improved by a factor of 1.3 using a superblock technique. Design for testability is primarily built-in test using a scan path method.