Showing papers on "Design for testing published in 1988"

SOCRATES: a highly efficient automatic test pattern generation system

Abstract: An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >

Testing and diagnosis of interconnects using boundary scan architecture

Abstract: A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes. >

Design for testability of mixed signal integrated circuits

Abstract: A starting point for a set of design for testability (DFT) principles that can be used with mixed signal integrated circuits is presented. The authors argue that an effective DFT technique should enhance the ability to perform digital signal processing and other modern test techniques on analog macros embedded in the integrated circuit, since quality will be a driving force with increasing integration. The proposed test methodology consists of (1) establishing the digital test model for testing of digital logic and (2) establishing the analog test mode and each of the submodes (called test configurations) for serial or parallel testing of analog partitions. Digital and analog circuitry must be isolated from each other, i.e. an uncontrolled analog signal must not be able to affect the digital test mode and vice versa. >

Circular BIST with partial scan

Abstract: A BIST (built-in self test) methodology that uses the circular BIST technique to perform a random test of sequential logic circuits is presented. The fault coverage obtained using this technique is supplemented by deterministic tests that are presented to the CUT (circuit under test) by configuring the circular path as a partial scan chain. A CAD (computer-aided-design) tool for automating this methodology is described, a variety of heuristics for picking which flip-flops should be included in the circular path are evaluated, and experimental results are presented. >

Test generation for data-path logic: the F-path method

Abstract: Tests for data-path logic can be generated with the aid of high-level methods that utilize the presence of special forms of sensitized paths. These paths, called fault paths (F-paths), are defined so that they transmit fault information with certainty. Their presence can be determined from the functional definition of a block, and when, exceptionally, they are absent, a minimum hardware addition usually suffices to provide them. They permit use of powerful, computer-aided test generation methods that have permitted routine targeting of 100% coverage of an expanded fault set (more than just stuck-ats), verification of success by simple postprocessing of RTL (resistor-transistor logic)-level good-logic simulation. >

Design for testability for mixed analog/digital ASICs

Abstract: A description is given of the concept and issues of design for testability for mixed analog-digital circuits, an architecture for testable circuits of this type, general testing procedure, and the concept of analog test tables. The analog test tables contain information such as what parameters are selected for testing, what nodes need to be accessible, and testing conditions. >

Design for testability

Abstract: This paper presents an implemented system for modifying digital circuit designs to enhance testability. The key contributions of the work are: (1) setting design for testability in the context of test generation, (2) using failures during test generation to focus on testability problems, (3) indexing from these failures to a set of suggested circuit modifications. This approach does not add testability features to the portions of the circuit that a test generator can already handle, therefore, it promises to reduce the area and performance overhead necessary to achieve testability. While the system currently has only a small body of domain knowledge, it has demonstrated its ability to integrate different DFT techniques and to introduce only sharply focused modifications on a textbook microprocessor, an ability that is missing in previous DFT systems.

Fault Detection and Design For Testability of CMOS Logic Circuits

Abstract: Advances in integrated circuit technologies have made complementary MOS (CMOS) the preferred MOS technology for digital logic circuits. Cost effective design and fabrication of reliable CMOS VLSI chips require understanding of various CMOS technologies, logic families, failure modes, fault detection methods and design for testability methods. In this paper we will review some of the basic methods and issues related to the design and fault detection of CMOS logic circuits.

VLSI design synthesis with testability

Abstract: A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom up and top down tree algorithms provide datapath allocation, constraint estimation, and feedback for design exploration. The partitioning and two dimensional characteristics of the binary tree structure provide VLSI design floorplans and global information for test incorporation. An elliptical wave filter example was used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple chain scan paths and BIST with different test schedules were explored. Design Scores comprised of area, delay, fault coverage, and test length were computed and graphed. Results show that the 'best' testable design solution is not always the same as that obtained from the 'best' design solution of an area and delay based synthesis search.

An automated BIST approach for general sequential logic synthesis

Abstract: An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%. >

A test and maintenance controller for a module containing testable chips

Abstract: A design of a module test and maintenance controller (MMC) is presented. Driven by structured test programs, an MMC is able to test every chip in a module via an ETM-BUS or a boundary scan bus. More than one test bus can be controlled by an MMC. MMC processor instructions, when executed, produce bus timing sequences which control a chip's BIT structures. The proposed MMC is a universal design. The difference between MMCs on different modules is the test programs which they executed and the number of test buses they control. Performance analysis indicates that either a RISC (reduced-instruction-set computer)-type processor or DMA controller is required in the MMC. Some self-test features of the MMC are also presented. >

Automatic insertion of BIST hardware using VHDL

Abstract: A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system. >

TRAM: a design methodology for high-performance, easily testable, multimegabit RAMs

Abstract: An architecture is proposed for multimegabit dynamic RAMs (random-access memories) that achieves higher testability and performance than the conventional four-quadrant RAMs. Applying the principle of divide and conquer, the RAM is partitioned into modules, each appearing as the leaf node of a binary interconnect network. Such a network carries the address/data/control bus, permitting the nodes to communicate among themselves as well as with the outside world. This architecture is shown to be easily testable. Parallelism in testing and partial self-test result in a large savings of testing time; the savings is independent of the test algorithm used. Unlike other testability schemes, this approach promises improved performance with only a small increase in chip area. It is also shown that the architecture is easily partionable and restructurable, with potential for yield and reliability improvement. >

A testable CMOS signal processor for fast Fourier transforms

Abstract: The authors present the architecture of a fast Fourier transform processor which has high performance characteristics and an embedded test structure that allows the processor to test itself during normal operation. The properties of separable residue codes have been used for error detection in the arithmetic unit of the processor. Offline error detection which tests for the classic stuck at faults is based on the properties of the dynamic CMOS logic design used. The testing circuitry used in the architecture accounts for only a 20% area overhead and no time ahead, an important saving in a signal-processing environment. >

Experiences gained using the Navy's IDSS weapon system testability analyzer

Abstract: The weapon system testability analyzer (WSTA), which has the ability to measure the testability of a design by modeling the actual process used during online, real-time fault diagnosis, is described. The results of experiences gained applying the ESTA to various levels of analysis are presented, including: built-in test (BIT) assessment at the organizational level; verification of complete testability from system, subsystem, and weapon replacable assembly (or line-replaceable unit) levels; and, through card-level testability, detection and isolation accurately and efficiently at the piece-part level. The ease of modeling, the reports generated and their usefulness to the testability process, and the unique features associated with the use of the tool are discussed. >

Design for testability of a 32-bit microprocessor-the TX1

Abstract: Testable designs of the TX1, a 32-bit microprocessor based on the TRON architecture, are described. Clear testing strategies were developed, resulting in three testable design approaches implemented in an optimized form. Logic function test is composed of scan test and self test. Their efficiency is highly enhanced by the use of the bus structure or microinstruction set of the TX1. Fault coverage of over 90% is achieved by them with short testing time (several seconds) and small increase of chip area (4.2%). Design verification is done with scan test and macroblock test. The latter can directly test important manually designed hardware blocks independent of the complicated decode and control logic. The area increase is only 0.4%. It can give useful information for their refinement in the early phase of development. >

The loophole in logic test: mixed signal ASIC

Abstract: The author surveys test-related loopholes that could limit mixed signals. All the loopholes are related to one or more of three fundamental environmental characteristics. First, mixed-signal ASIC (application-specific integrated circuit) components lack the controllability and observability seen at old component/card test levels. Second, there is much closer interaction between the logic and analog portions of a design. Third, design and product life cycles are being compressed to the point where existing card and component test methodologies and processes no longer meet requirements. He shows that the key development that will lead to significant improvements in mixed signal test methodologies is the most recent generation of mixed-signal, digital signal processor (DSP)-based tester/work stations. Particularly important is computer-automated design software that these systems provide, which may establish a better environment for design-for-test and test generation development. >

Testing word oriented embedded RAMs using built-in self test

Abstract: The author presents a built-in self test method for word-oriented embedded static RAMs. Based on bit-oriented march tests, which are very suitable for self-test applications, word-oriented extensions are presented and analyzed for fault coverage. The self-test algorithm gives a high fault coverage for digital faults. Besides simple stuck-at faults, it detects transition faults and multiple-access faults. Also, all two-coupling faults between arbitrary pairs of cells are detected, so no knowledge of the physical placement of the cells is required. A prototype of the hardware implementation of the BIST method shows that the overhead, especially for large RAMs, is quite modest. The self-test hardware can be parameterized to size, making automatic generation by a module compiler easy. >

Pseudoexhaustive test pattern generator with enhanced fault coverage

Abstract: A method of pseudoexhaustive test pattern generation is proposed that is suitable above all for circuits using random access scan. Two linear feedback shift registers are used to generate scan addresses and test patterns to be scanned into these addresses. It is shown that the method gives better results than random testing. >

Reconfigurable hardware for pseudoexhaustive test

Abstract: The designs of two test pattern generators for pseudoexhaustive testing have been presented. These designs are capable of implementing test sets (recipe cubes) that exhaustively test the segments of a circuit. The application of each test set requires two control bits per circuit input. The test-pattern generators can be reconfigured by simple control circuitry to apply each of the test sets of a pseudoexhaustive test in sequence. The first design, based on multiplexers, uses very little hardware. The second design is a reconfigurable counter. Both of the designs presented can be used with built-in self-test (BIST) and or scan-path testing. In addition to higher fault coverage than single stuck-at testing, the use of these designs can sometimes offer reduced on-chip storage requirements and reduced testing time. >

ESTA: an expert system for DFT rule verification

Abstract: A description is given of ESTA, an expert system for the automation of design for testability (DFT) verification. The system takes descriptions written in a conventional hardware description language as input, translates them into a intermediate Prolog form and checks whether they comply either with the level sensitive scan design (LSSD) DFT method of B. Eichelberger and T.W. Williams (1977) or the built-in logic block observation (BILBO) DFT techniques of B. Konemann et al. (1979). >

Implementation of VLSI self-testing by regularization

Abstract: A novel circuit design methodology is developed for comprehensive offline self-testing of nearly regular VLSI circuits. It is based on four major design techniques: circuit partitioning, regularization to produce identical subcircuits (modules), parallel testing of modules, and fault detection by direct comparison of response streams from the modules. A generalization of I-testing called sequential I-testing (SI-testing) is described, which allows identical response streams to be produced at different times and be subsequently synchronized for comparison purposes. The concepts of k-regular and nearly k-regular circuits are introduced, which generalize regular circuits (iterative logic arrays) to array-like circuits that contain several cell-types and are moderately irregular. A heuristic circuit partitioning and regularization method for nearly-regular circuits is described. >

Emitter coupled logic and cascode current switch testability and design for test

Abstract: Application-specific integrated circuits (ASICs) are frequently utilized in applications demanding the highest circuit performance. Gate delays under 300 ps are now achievable using emitter coupled logic (ECL) and cascode current switch (CCS). However, as performance increases, so does the difficulty and cost of testing for quality parts. The design and operation of ECL and CCS and their sensitivities to chip failure mechanisms are discussed. By applying DC-level shifts to the internal signals, these faults can become testable. An approach to the design and test of these gates which enhances the testability of both AC and DC defects is given. >

A modular scan-based testability system

Abstract: The authors present a scan-based testability system that is an integral part of the cell-based design system at Microelectronics Center of North Carolina. The basic system consists of five modules: a scan-based audit to verify compliance with scan-based rules, a testability assessment module that projects fault coverage before any patterns are applied, a fast fault simulator that grades random and user-supplied patterns, an algorithmic test-pattern generator that produces test for faults that resist detection with random patterns or declares them redundant, and a test-pattern compactor to further reduce the size of the test-pattern set. The system serves as a platform for research into hierarchical methods, redundancy identification and removal, automated test point insertion, improved random test pattern generation, fault simulation, and boundary scan. >

Structural way of thinking as applied to high quality design

Abstract: The authors attempt to clarify the principle involved in achieving high-quality design. The nature of human errors inherent in software and hardware design is summarized. A structural method of thinking introduced previously is described and used as a basis for high-quality design. >

Conditionally robust two-pattern tests and CMOS design for testability

Abstract: The concept of a conditionally robust two-pattern test for testing stuck-open transistor faults in CMOS gates is introduced. Such a test is conditionally hazard-free; i.e. the transition will not produce a hazardous output provided a (partial) order is imposed on the time instants at which the components of the input pattern undergo transition. Two sources of the existence of such a partial order are identified: (1) when a set of transistors is controlled by the same logic signal, the symbolic layout (routing) information provides the knowledge of such a partial order; and (2) multipattern tests, which may be necessary to test embedded CMOS gates, can be looked upon as two-pattern tests with an imposed partial order. Algorithms are given to determine whether a two-pattern test is conditionally hazard-free under a given partial order and to compute minimal cardinality partial orders that, when imposed on a transition, make it conditionally hazard-free. >

A testable CMOS synchronous counter

Abstract: A testable design of a CMOS synchronous counter is presented with test vectors that provide 100% coverage of stuck-at and stuck-open faults in a time of order L/sup 2/, where L is the bit length of the counter. This design is made compatible with the scan design methodology by incurring minimal hardware overhead which is also fully testable for the above faults. Test application time is shown to be strongly dependent on observability of the counter outputs and can be considerably reduced if the outputs are directly observable without having to scan the test results out. The authors develop a signal flow model for the counter, based on which, test vectors are derived and proved to provide complete coverage of the above faults. The design is also superior in that its operating speed is only limited by a single inverter delay, found to be 1-4 ns per bit slice, depending on the CMOS process. Furthermore, this speed is not affected by the addition of scan circuitry. >